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Merge pull request #599 from trabucayre/sipeed_tang_gw5A_SDRAM
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Sipeed tang gw5 a sdram
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@enjoy-digital
enjoy-digital authored Aug 19, 2024
2 parents a950450 + b1a6da8 commit 52fc033
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Showing 4 changed files with 185 additions and 24 deletions.
68 changes: 51 additions & 17 deletions litex_boards/platforms/sipeed_tang_mega_138k_pro.py
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Original file line number Diff line number Diff line change
Expand Up @@ -243,23 +243,6 @@
Misc("PULL_MODE=NONE DRIVE=8")
),

("sdram_clock", 0, Pins("V23"), IOStandard("LVCMOS33")),
("sdram", 0,
Subsignal("a", Pins(
"V19 W19 U22 V22 Y25 AA25 AA24 AB25",
"AB26 AC26 Y20 U25 U24")),
Subsignal("dq", Pins(
"U16 V16 U15 V17 W21 Y21 P21 U17",
"P25 W23 T25 R25 R23 T23 P24 P23")),
Subsignal("ba", Pins("V26 W20")),
Subsignal("cas_n", Pins("W26")),
Subsignal("cs_n", Pins("U26")),
Subsignal("ras_n", Pins("W25")),
Subsignal("we_n", Pins("Y26")),
IOStandard("LVCMOS33"),
Misc("PULL_MODE=UP")
),

# RGMII Ethernet
("eth_clocks", 0,
Subsignal("tx", Pins("H24")),
Expand Down Expand Up @@ -294,6 +277,57 @@
],
]

# SDRAMs -------------------------------------------------------------------------------------------

def misterSDRAM(conn="sdram_connector"):
return [
("sdram_clock", 0, Pins(f"{conn}:20"),
IOStandard("LVCMOS33"),
Misc("PULL_MODE=NONE DRIVE=16"),
),
("sdram", 0,
Subsignal("a", Pins(
f"{conn}:37 {conn}:38 {conn}:39 {conn}:40 {conn}:28 {conn}:25 {conn}:26 {conn}:23",
f"{conn}:24 {conn}:21 {conn}:36 {conn}:22 {conn}:19"),
),
Subsignal("dq", Pins(
f"{conn}:1 {conn}:2 {conn}:3 {conn}:4 {conn}:5 {conn}:6 {conn}:7 {conn}:8",
f"{conn}:18 {conn}:17 {conn}:16 {conn}:15 {conn}:14 {conn}:13 {conn}:10 {conn}:9"),
),
Subsignal("ba", Pins(f"{conn}:34 {conn}:35")),
Subsignal("cas_n", Pins(f"{conn}:31")),
Subsignal("cs_n", Pins(f"{conn}:33")),
Subsignal("ras_n", Pins(f"{conn}:32")),
Subsignal("we_n", Pins(f"{conn}:27")),
IOStandard("LVCMOS33"),
),
]

def sipeedSDRAM(conn="sdram_connector"):
return [
("sdram_clock", 0, Pins(f"{conn}:20"),
IOStandard("LVCMOS33"),
Misc("PULL_MODE=NONE DRIVE=16"),
),
("sdram", 0,
Subsignal("a", Pins(
f"{conn}:37 {conn}:38 {conn}:39 {conn}:40 {conn}:28 {conn}:25 {conn}:26 {conn}:23",
f"{conn}:24 {conn}:21 {conn}:36 {conn}:22 {conn}:19")
),
Subsignal("dq", Pins(
f"{conn}:1 {conn}:2 {conn}:3 {conn}:4 {conn}:5 {conn}:6 {conn}:7 {conn}:8",
f"{conn}:18 {conn}:17 {conn}:16 {conn}:15 {conn}:14 {conn}:13 {conn}:10 {conn}:9"),
),
Subsignal("ba", Pins(f"{conn}:34 {conn}:35")),
Subsignal("cas_n", Pins(f"{conn}:31")),
Subsignal("cs_n", Pins(f"{conn}:33")),
Subsignal("ras_n", Pins(f"{conn}:32")),
Subsignal("we_n", Pins(f"{conn}:27")),
Subsignal("dm", Pins(f"{conn}:29 {conn}:30")),
IOStandard("LVCMOS33"),
),
]

# Platform -----------------------------------------------------------------------------------------

class Platform(GowinPlatform):
Expand Down
52 changes: 52 additions & 0 deletions litex_boards/platforms/sipeed_tang_primer_25k.py
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Original file line number Diff line number Diff line change
Expand Up @@ -126,6 +126,57 @@
}),
]

# SDRAMs -------------------------------------------------------------------------------------------

def misterSDRAM(conn="j3"):
return [
("sdram_clock", 0, Pins(f"{conn}:20"),
IOStandard("LVCMOS33"),
Misc("PULL_MODE=NONE DRIVE=16"),
),
("sdram", 0,
Subsignal("a", Pins(
f"{conn}:37 {conn}:38 {conn}:39 {conn}:40 {conn}:28 {conn}:25 {conn}:26 {conn}:23",
f"{conn}:24 {conn}:21 {conn}:36 {conn}:22 {conn}:19")
),
Subsignal("dq", Pins(
f"{conn}:1 {conn}:2 {conn}:3 {conn}:4 {conn}:5 {conn}:6 {conn}:7 {conn}:8",
f"{conn}:18 {conn}:17 {conn}:16 {conn}:15 {conn}:14 {conn}:13 {conn}:10 {conn}:9")
),
Subsignal("ba", Pins(f"{conn}:34 {conn}:35")),
Subsignal("cas_n", Pins(f"{conn}:31")),
Subsignal("cs_n", Pins(f"{conn}:33")),
Subsignal("ras_n", Pins(f"{conn}:32")),
Subsignal("we_n", Pins(f"{conn}:27")),
IOStandard("LVCMOS33"),
),
]

def sipeedSDRAM(conn="j3"):
return [
("sdram_clock", 0, Pins(f"{conn}:20"),
IOStandard("LVCMOS33"),
Misc("PULL_MODE=NONE DRIVE=16"),
),
("sdram", 0,
Subsignal("a", Pins(
f"{conn}:37 {conn}:38 {conn}:39 {conn}:40 {conn}:28 {conn}:25 {conn}:26 {conn}:23",
f"{conn}:24 {conn}:21 {conn}:36 {conn}:22 {conn}:19")
),
Subsignal("dq", Pins(
f"{conn}:1 {conn}:2 {conn}:3 {conn}:4 {conn}:5 {conn}:6 {conn}:7 {conn}:8",
f"{conn}:18 {conn}:17 {conn}:16 {conn}:15 {conn}:14 {conn}:13 {conn}:10 {conn}:9"),
),
Subsignal("ba", Pins(f"{conn}:34 {conn}:35")),
Subsignal("cas_n", Pins(f"{conn}:31")),
Subsignal("cs_n", Pins(f"{conn}:33")),
Subsignal("ras_n", Pins(f"{conn}:32")),
Subsignal("we_n", Pins(f"{conn}:27")),
Subsignal("dm", Pins(f"{conn}:29 {conn}:30")),
IOStandard("LVCMOS33"),
),
]

# Platform -----------------------------------------------------------------------------------------

class Platform(GowinPlatform):
Expand All @@ -139,6 +190,7 @@ def __init__(self, toolchain="gowin"):
self.add_connector(_dock_connectors)

self.toolchain.options["use_mspi_as_gpio"] = 1 # spi flash
self.toolchain.options["use_i2c_as_gpio"] = 1 # SDRAM / J3
self.toolchain.options["use_ready_as_gpio"] = 1 # led
self.toolchain.options["use_done_as_gpio"] = 1 # led
self.toolchain.options["use_cpu_as_gpio"] = 1 # clk
Expand Down
22 changes: 20 additions & 2 deletions litex_boards/targets/sipeed_tang_mega_138k_pro.py
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Original file line number Diff line number Diff line change
Expand Up @@ -22,7 +22,7 @@

from liteeth.phy.gw5rgmii import LiteEthPHYRGMII

from litedram.modules import AS4C32M16, MT41J256M16
from litedram.modules import AS4C32M16, MT41J256M16, W9825G6KH6
from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY
from litedram.phy import GW5DDRPHY
from litex.build.io import DDROutput
Expand Down Expand Up @@ -122,13 +122,22 @@ def __init__(self, sys_clk_freq=50e6,
with_video_terminal = False,
with_ddr3 = False,
with_sdram = False,
sdram_model = "sipeed",
sdram_rate = "1:2",
with_led_chaser = True,
with_rgb_led = False,
with_buttons = True,
**kwargs):
platform = sipeed_tang_mega_138k_pro.Platform(toolchain="gowin")

assert not with_sdram or (sdram_model in ["sipeed", "mister"])

if with_sdram:
platform.add_extension({
"sipeed": sipeed_tang_mega_138k_pro.sipeedSDRAM(),
"mister": sipeed_tang_mega_138k_pro.misterSDRAM}[sdram_model]
)

# CRG --------------------------------------------------------------------------------------
cpu_clk_freq = int(800e6) if kwargs["cpu_type"] == "gowin_ae350" else 0
self.crg = _CRG(platform, sys_clk_freq, cpu_clk_freq,
Expand Down Expand Up @@ -207,14 +216,17 @@ def __init__(self, sys_clk_freq=50e6,

# SDR SDRAM --------------------------------------------------------------------------------
if with_sdram and not self.integrated_main_ram_size:
module_cls = {
"sipeed": W9825G6KH6,
"mister": AS4C32M16}[sdram_model]
if sdram_rate == "1:2":
sdrphy_cls = HalfRateGENSDRPHY
else:
sdrphy_cls = GENSDRPHY
self.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq)
self.add_sdram("sdram",
phy = self.sdrphy,
module = AS4C32M16(sys_clk_freq, sdram_rate),
module = module_cls(sys_clk_freq, sdram_rate),
l2_cache_size = kwargs.get("l2_size", 8192)
)

Expand All @@ -226,6 +238,11 @@ def main():
parser.add_target_argument("--flash", action="store_true", help="Flash Bitstream.")
parser.add_target_argument("--sys-clk-freq", default=50e6, type=float, help="System clock frequency.")
parser.add_target_argument("--with-sdram", action="store_true", help="Enable optional SDRAM module.")
parser.add_target_argument("--sdram-model", default="sipeed", help="SDRAM module model.",
choices=[
"sipeed",
"mister"
])
parser.add_target_argument("--with-ddr3", action="store_true", help="Enable optional DDR3 module.")
parser.add_target_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (HDMI).")
ethopts = parser.target_group.add_mutually_exclusive_group()
Expand All @@ -243,6 +260,7 @@ def main():
with_video_terminal = args.with_video_terminal,
with_ddr3 = args.with_ddr3,
with_sdram = args.with_sdram,
sdram_model = args.sdram_model,
with_ethernet = args.with_ethernet,
with_etherbone = args.with_etherbone,
local_ip = args.local_ip,
Expand Down
67 changes: 62 additions & 5 deletions litex_boards/targets/sipeed_tang_primer_25k.py
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Original file line number Diff line number Diff line change
Expand Up @@ -10,21 +10,32 @@

from litex.gen import *

from litex.build.io import DDROutput

from litex.soc.cores.clock.gowin_gw5a import GW5APLL
from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import *
from litex.soc.cores.led import LedChaser
from litex.soc.cores.gpio import GPIOIn

from litedram.modules import AS4C32M16, W9825G6KH6
from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY

from litex_boards.platforms import sipeed_tang_primer_25k

# CRG ----------------------------------------------------------------------------------------------

class _CRG(LiteXModule):
def __init__(self, platform, sys_clk_freq):
def __init__(self, platform, sys_clk_freq, with_sdram=False, sdram_rate="1:2"):
self.rst = Signal()
self.cd_sys = ClockDomain()
self.cd_por = ClockDomain()
if with_sdram:
if sdram_rate == "1:2":
self.cd_sys2x = ClockDomain()
self.cd_sys2x_ps = ClockDomain()
else:
self.cd_sys_ps = ClockDomain()

# # #

Expand All @@ -46,23 +57,61 @@ def __init__(self, platform, sys_clk_freq):
pll.register_clkin(clk50, 50e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)

# SDRAM clock
if with_sdram:
if sdram_rate == "1:2":
pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq)
pll.create_clkout(self.cd_sys2x_ps, 2*sys_clk_freq, phase=180)
sdram_clk = ClockSignal("sys2x_ps")
else:
pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
sdram_clk = ClockSignal("sys_ps")
self.specials += DDROutput(1, 0, platform.request("sdram_clock"), sdram_clk)

# BaseSoC ------------------------------------------------------------------------------------------

class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=50e6,
with_spi_flash = False,
with_led_chaser = True,
with_buttons = True,
with_sdram = False,
sdram_model = "sipeed",
sdram_rate = "1:2",
**kwargs):

platform = sipeed_tang_primer_25k.Platform(toolchain="gowin")

assert not with_sdram or (sdram_model in ["sipeed", "mister"])

if with_sdram:
platform.add_extension({
"sipeed": sipeed_tang_primer_25k.sipeedSDRAM(),
"mister": sipeed_tang_primer_25k.misterSDRAM}[sdram_model]
)

# CRG --------------------------------------------------------------------------------------
self.crg = _CRG(platform, sys_clk_freq)
self.crg = _CRG(platform, sys_clk_freq, with_sdram, sdram_rate)

# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Tang Primer 25K", **kwargs)

# SDR SDRAM --------------------------------------------------------------------------------
if with_sdram and not self.integrated_main_ram_size:
module_cls = {
"sipeed": W9825G6KH6,
"mister": AS4C32M16}[sdram_model]
if sdram_rate == "1:2":
sdrphy_cls = HalfRateGENSDRPHY
else:
sdrphy_cls = GENSDRPHY
self.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq)
self.add_sdram("sdram",
phy = self.sdrphy,
module = module_cls(sys_clk_freq, sdram_rate),
l2_cache_size = kwargs.get("l2_size", 8192)
)

# SPI Flash --------------------------------------------------------------------------------
if with_spi_flash:
from litespi.modules import W25Q64FV as SpiFlashModule
Expand All @@ -86,14 +135,22 @@ def __init__(self, sys_clk_freq=50e6,
def main():
from litex.build.parser import LiteXArgumentParser
parser = LiteXArgumentParser(platform=sipeed_tang_primer_25k.Platform, description="LiteX SoC on Tang Primer 25K.")
parser.add_target_argument("--flash", action="store_true", help="Flash Bitstream.")
parser.add_target_argument("--sys-clk-freq", default=50e6, type=float, help="System clock frequency.")
parser.add_target_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
parser.add_target_argument("--flash", action="store_true", help="Flash Bitstream.")
parser.add_target_argument("--sys-clk-freq", default=50e6, type=float, help="System clock frequency.")
parser.add_target_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
parser.add_target_argument("--with-sdram", action="store_true", help="Enable optional SDRAM module.")
parser.add_target_argument("--sdram-model", default="sipeed", help="SDRAM module model.",
choices=[
"sipeed",
"mister"
])
args = parser.parse_args()

soc = BaseSoC(
sys_clk_freq = args.sys_clk_freq,
with_spi_flash = args.with_spi_flash,
with_sdram = args.with_sdram,
sdram_model = args.sdram_model,
**parser.soc_argdict
)
builder = Builder(soc, **parser.builder_argdict)
Expand Down

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