targets: Fix build with --cpu-type=None on iCE40/Up5kSPRAM.

litex-hub · Aug 28, 2024 · c5d1a25 · c5d1a25
1 parent 4002b81
commit c5d1a25
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Showing 4 changed files with 4 additions and 4 deletions.
diff --git a/litex_boards/targets/ice_v_wireless.py b/litex_boards/targets/ice_v_wireless.py
@@ -134,7 +134,7 @@ def __init__(self, bios_flash_offset, sys_clk_freq=24e6, revision="v0", with_led
 
         # 128KB SPRAM (used as 64kB SRAM / 64kB RAM) -----------------------------------------------
         self.spram = Up5kSPRAM(size=128 * KILOBYTE)
-        self.bus.add_slave("psram", self.spram.bus, SoCRegion(size=128 * KILOBYTE))
+        self.bus.add_slave("psram", self.spram.bus, SoCRegion(origin=self.mem_map["sram"], size=128 * KILOBYTE))
         self.bus.add_region("sram", SoCRegion(
                 origin = self.bus.regions["psram"].origin + 0 * KILOBYTE,
                 size   = 64 * KILOBYTE,

diff --git a/litex_boards/targets/icebreaker.py b/litex_boards/targets/icebreaker.py
@@ -82,7 +82,7 @@ def __init__(self, bios_flash_offset, sys_clk_freq=24e6,
 
         # 128KB SPRAM (used as 64kB SRAM / 64kB RAM) -----------------------------------------------
         self.spram = Up5kSPRAM(size=128 * KILOBYTE)
-        self.bus.add_slave("psram", self.spram.bus, SoCRegion(size=128 * KILOBYTE))
+        self.bus.add_slave("psram", self.spram.bus, SoCRegion(origin=self.mem_map["sram"], size=128 * KILOBYTE))
         self.bus.add_region("sram", SoCRegion(
                 origin = self.bus.regions["psram"].origin + 0 * KILOBYTE,
                 size   = 64 * KILOBYTE,

diff --git a/litex_boards/targets/icebreaker_bitsy.py b/litex_boards/targets/icebreaker_bitsy.py
@@ -113,7 +113,7 @@ def __init__(self, bios_flash_offset, sys_clk_freq=24e6, revision="v1", with_led
 
         # 128KB SPRAM (used as 64kB SRAM / 64kB RAM) -----------------------------------------------
         self.spram = Up5kSPRAM(size=128 * KILOBYTE)
-        self.bus.add_slave("psram", self.spram.bus, SoCRegion(size=128 * KILOBYTE))
+        self.bus.add_slave("psram", self.spram.bus, SoCRegion(origin=self.mem_map["sram"], size=128 * KILOBYTE))
         self.bus.add_region("sram", SoCRegion(
                 origin = self.bus.regions["psram"].origin + 0 * KILOBYTE,
                 size   = 64 * KILOBYTE,

diff --git a/litex_boards/targets/kosagi_fomu.py b/litex_boards/targets/kosagi_fomu.py
@@ -85,7 +85,7 @@ def __init__(self, bios_flash_offset, sys_clk_freq=12e6,
 
         # 128KB SPRAM (used as 64kB SRAM / 64kB RAM) -----------------------------------------------
         self.spram = Up5kSPRAM(size=128 * KILOBYTE)
-        self.bus.add_slave("psram", self.spram.bus, SoCRegion(size=128 * KILOBYTE))
+        self.bus.add_slave("psram", self.spram.bus, SoCRegion(origin=self.mem_map["sram"], size=128 * KILOBYTE))
         self.bus.add_region("sram", SoCRegion(
                 origin = self.bus.regions["psram"].origin + 0 * KILOBYTE,
                 size   = 64 * KILOBYTE,