firtool-1.66.0

What's Changed

• [HW] Lower hw.instance_choice to SV by @nandor in #6624
• [ESI][Runtime] Convert Type& to Type* by @teqdruid in #6644
• [ESI][Runtime][NFC] Move requestChannelsFor into accelerator connection by @teqdruid in #6646
• [ESI][Runtime] Add the notion of a Context by @teqdruid in #6647
• [ESI][Runtime][NFC] Switch from ptr,size to MessageData by @teqdruid in #6648
• Fix some issues in the LayerBlockOp verifier by @rwy7 in #6654
• [FIRRTL] Use set-based logic to test for layer compatibility by @rwy7 in #6643
• [FIRRTL] Intrinsics: Fix mistakenly preserved analyses. by @dtzSiFive in #6666
• [OM] Remove Symbol trait from ClassFieldLikes. by @mikeurbach in #6665
• [Calyx] Make ControlOp a SymbolTable. by @mikeurbach in #6670
• [IMCP] Fix a race condition regarding aggregate preservation by @uenoku in #6671
• Track instance layers by @rwy7 in #6663
• [CI] Add statically linked CIRCT full build to ReleaseArtifact CI by @uenoku in #6544
• [FIRRTL] chisel_{assert_assume,assume,cover,ifelsefatal} intrinsics. by @dtzSiFive in #6664
• [ImportVerilog] Add import options and Verilog preprocessing by @fabianschuiki in #6632
• Allow propassign under layerblocks by @rwy7 in #6656
• [Seq] Remove Symbol trait from HLMemOp. by @mikeurbach in #6676
• [ESI][Runtime] Adding support for FuncService by @teqdruid in #6673
• [FIRRTL] InferResets: verify that FART annotation is on async resets by @youngar in #6674
• [FSM] Remove Symbol trait from InstanceOp and HWInstanceOp. by @mikeurbach in #6675
• [FIRRTL][LowerXMR] Use FIRRTL 4.0 ref ABI. by @dtzSiFive in #6677
• Tree-wide test fixes for FileCheck directive typos by @dtzSiFive in #6679
• [LowerIntrinsics] Accept EICG_wrapper without test_en, reject annos by @fabianschuiki in #6678
• [WireDFT] Disable the pass by default by @nandor in #6684
• [LowerToHW] Fix shr(0-bit, n) lowering by @seldridge in #6683
• [ImportVerilog] Fix single unit preprocessor option by @fabianschuiki in #6682
• [arcilator] Remove PrintStateInfo pass by @Moxinilian in #6529
• LLVM bump by @darthscsi in #6662
• Make circt-verilog available to integration tests. by @dtzSiFive in #6685
• [LowerClasses] Lower classes that instantiate properties. by @mikeurbach in #6688
• [FIRRTL] Add layer-associated Probes to LowerLayers pass by @seldridge in #6554
• [ExportVerilog] Fix crash on sv.reg with initial value by @fzi-hielscher in #6689
• [HW] Encode the option group name in instance choice ops by @nandor in #6645
• [HW] HWModule: store input port locations only on block args by @youngar in #6642
• [FIRRTL] Add parser version APIs that accept an SMLoc, NFC. by @mikeurbach in #6692
• [FIRRTL] Provide a way to override inferReturnTypes in FIRRTLExprOp. by @mikeurbach in #6697
• [FIRRTL] Add integer addition property op. by @mikeurbach in #6691
• [OM] Add rationale for expressions. by @mikeurbach in #6702
• [OM] Add OpInterface for IntegerBinaryArithmeticOp. by @mikeurbach in #6703
• [PyCDE] Refactor Input/Output ports to extend property by @teqdruid in #6700
• [FIRRTL] Add integer addition parser support. by @mikeurbach in #6701
• [CMake] Make ImportVerilog compile-time depend on slang by @fzi-hielscher in #6707
• [FIRRTL][Lower-Layers] do not capture uses multiple times by @rwy7 in #6699
• [FIRRTL] Change min width of shr for UInt to 0 by @jackkoenig in #6698
• [FIRRTL] Use untyped propassign source accessor in LowerClasses. by @mikeurbach in #6690
• [OM] Add integer addition op. by @mikeurbach in #6704

New Contributors

• @Moxinilian made their first contribution in #6529

Full Changelog: firtool-1.65.0...firtool-1.66.0