firtool-1.67.0

What's Changed

• [LLVM] Bump by @nandor in #6718
• [FIRRTL] Update HierPathOps in LowerLayers by @seldridge in #6721
• [ESI][Runtime] Use std::future in channel reads and func calls by @teqdruid in #6723
• [FIRRTL] Add integer addition conversion to LowerClasses. by @mikeurbach in #6710
• [OM] Support integer binary arithmetic in the Evaluator. by @mikeurbach in #6711
• [FIRTOOL] More sane chisel interface directory handling by @darthscsi in #6687
• [FIRRTL] Prevent divison by zero in CreateSiFiveMetadata by @fzi-hielscher in #6726
• [ImportVerilog] Add translation, run Slang compilation by @fabianschuiki in #6708
• [FIRRTL] Support PropertyType in emitConnect. by @mikeurbach in #6734
• [PyCDE] Wrappers for Ibis classes by @teqdruid in #6631
• [FIRRTL] Check unknown width and reset rules during parsing 4.0.0. by @dtzSiFive in #6731
• [Sim] Introduce wrappers on top of sv.finish/sv.fatal by @nandor in #6737
• [FIRRTL][CAPI] Add function for importing annotations by @SpriteOvO in #6730
• [Emit] Organize output files using the emit dialect by @nandor in #6727
• [ExportVerilog][Emit] Export emitted files by @nandor in #6728
• [Emit] Emit black boxes through emit ops by @nandor in #6729
• [ImportVerilog] Convert empty modules and instances by @fabianschuiki in #6743
• [FIRRTL][LowerLayers] Clean up names of artifacts generated by layers by @rwy7 in #6733
• [Ibis] Split ContainerOp in two by @teqdruid in #6739
• [Emit] Emit SV ops nested in a file by @nandor in #6744
• [FIRRTL][FIRParser] Enforce 4.0.0 main module must be public. by @dtzSiFive in #6747
• [Emit] Use FileOp to emit metadata by @nandor in #6746
• [MSFT][Emit] Replace output_file with an emit::File by @nandor in #6751
• [Emit] Convert the ExtractInstances pass to use file ops by @nandor in #6756
• [ExtractInstances] Fix Windows CI by @nandor in #6758
• [HGLDD] Fix instance output port emission by @fabianschuiki in #6750
• [HGLDD] Uniquify object names during emission by @fabianschuiki in #6753
• [HW to BTOR2] Add support for initial values by @dobios in #6754
• [ImportVerilog] Add type conversion and basic variables by @fabianschuiki in #6755
• [ESI][Runtime] Building wheels by @teqdruid in #6759
• [HW] Remove the file list attribute from HW by @nandor in #6757
• [ESI][Runtime] Build and publish wheels by @teqdruid in #6763
• [FIRRTL] Put layer collateral in testbench dir by @seldridge in #6741
• [ESI] Move entirely over to the runtime for testing by @teqdruid in #6764
• [Emit] Introduce emit.ref to pull ops into file bodies by @nandor in #6762
• [Calyx] Switch sequential memories to be true single port memories by @andrewb1999 in #6765
• [ImportVerilog] Convert initial/always/final procedures by @fabianschuiki in #6766
• [Calyx] Fix memory import locations by @andrewb1999 in #6769
• [arcilator] Introduce simulation orchestration subdialect by @Moxinilian in #6695
• [FIRRTL] Use the class map in ObjectOp parser. by @mikeurbach in #6771
• [capi][python] Add Emit Dialect by @seldridge in #6774

Full Changelog: firtool-1.66.0...firtool-1.67.0