firtool-1.108.0

What's Changed

• [MemoryBanking] Should not overwrite banking factor/dimension when resolving attribute values by @jiahanxie353 in #8267
• [LLHD] Add dedicated Mem2Reg pass by @fabianschuiki in #8244
• [ESI][XRT] Implement "Indirect MMIO" by @teqdruid in #8273
• [ImportVerilog] Add option to lower always @* as always_comb by @fabianschuiki in #8271
• [LLHD] Support conditional drives in mem2reg by @fabianschuiki in #8278
• [ESI][BSP] Simple ToHost DMA engine by @teqdruid in #8207
• [LLHD] Support drives with delta delay in mem2reg by @fabianschuiki in #8279
• [AffineParallelUnroll] Fix empty map lookup; move canonicalization passes before MemoryConflictResolver by @jiahanxie353 in #8282
• [circt-verilog-lsp-server] Add Verilog Language Server by @uenoku in #8234
• [SMT][CAPI] Add more SMT C API by @Clo91eaf in #8274
• [MemoryBanking] Memory banking supports multiple banking factors/dimensions config by @jiahanxie353 in #8277
• [Python] Declare a separate sub-target for support sources by @maerhart in #8243
• [sim] Add emission for plusargs for UPF simulations by @youngar in #8272

Full Changelog: firtool-1.107.0...firtool-1.108.0

firtool-1.107.0

What's Changed

• [Calyx] Unroll Affine ParallelOp to multiple SCF ExecuteRegionOps by @jiahanxie353 in #8248
• [Calyx] Change calyx.parallel to calyx.unroll in the test cases by @jiahanxie353 in #8251
• [Calyx] Canonicalize SCF IndexSwitch after AffineParallelUnroll by @jiahanxie353 in #8249
• [Calyx] virtual dtor to properly destruct derived classes by @dtzSiFive in #8252
• [SCFToCalyx] Update the lowering of SCF ParallelOp after AffineParallelUnroll pass by @jiahanxie353 in #8250
• [verif.contract] add sby integration test by @leonardt in #8237
• [Arcilator] Allow running verif.simulation ops by @fabianschuiki in #8233
• Bump LLVM for index CAPI by @maerhart in #8240
• [RTG] Add on_context and context_switch operations by @maerhart in #8150
• [RTG][Elaboration] Add support for context operations by @maerhart in #8151
• [RTG] Custom assembly format for 'rtg.test' operation by @maerhart in #8188
• [RTG] Add interleave_sequences op by @maerhart in #8189
• [RTG][Elaboration] Use malloc instead of IR for virtual registers and labels by @maerhart in #8194
• [RTG][Elaboration] Support interleave_sequences, factor our sequence inlining and label resolution by @maerhart in #8198
• [RTG][InlineSequences] Support interleave_sequences by @maerhart in #8199
• [RTG][CAPI] Expose getter for bag and set element type by @maerhart in #8227
• [PyRTG] Wrapper around SSA values and label support by @maerhart in #8228
• [PyRTG] Support sets by @maerhart in #8229
• [PyRTG] Support integers by @maerhart in #8235
• [PyRTG] Support bags by @maerhart in #8236
• [PyRTG] Support sequences by @maerhart in #8238
• [PyRTG] Support targets and test arguments by @maerhart in #8239
• [RTG] Move immediate type tablegen base to RTG dialect by @maerhart in #8242
• [PyRTG] Add immediates and registers by @maerhart in #8247
• [Verif] Change simulation exit code to success boolean by @fabianschuiki in #8253
• [LLHD][Sig2Reg] Support integer signal aliasing by @maerhart in #8261
• [FIRRTL] Add a folder for add property op by @mtsokol in #8200
• [circt-synth] Load dialects that firtool emits by @uenoku in #8257
• Bump LLVM to 6bfedfa0ba31a8ac8fd7fcfd2d33afaa5eabe0e5. by @mikeurbach in #8264
• [FIRRTL] Add folder for mul property op by @mtsokol in #8222
• [ExportSMTLIB] Implement ExportSMTLIB C API by @Clo91eaf in #8263
• [Calyx] LICM after Affine ParallelOp unrolling by @jiahanxie353 in #8256
• [FlattenMemRef] Flatten MemRef ReshapeOp when its source memory reference is flattened in other passes by @jiahanxie353 in #8265

New Contributors

• @mtsokol made their first contribution in #8200

Full Changelog: firtool-1.106.0...firtool-1.107.0

firtool-1.106.0

What's Changed

• [HW] Resolve ambiguous array_slice documentation by @maerhart in #8202
• [ESI][BSP] Bunch of small fixes and changes by @teqdruid in #8206
• [FIRRTL][LowerToHW] Lower contract ops by @fabianschuiki in #8159
• [circt-test] Add support for contracts by @fabianschuiki in #8166
• [MooreToCore]Fix a crash caused by block args as observed values for llhd.wait. by @hailongSun2000 in #8210
• [ImportVerilog] Fix assertion with constant folding by @likeamahoney in #8213
• [firtool] Add an option to emit HW MLIR into file by @uenoku in #8169
• [Verif] Mark SymbolicValueOp result as MemAlloc by @fabianschuiki in #8208
• [NFCI] Align cmake slightly more to mlir example by @darthscsi in #8217
• [RTG] Move immediates to RTG from RTGTest by @darthscsi in #8216
• [Moore] Mark wait_event with side-effect even if it is empty by @maerhart in #8220
• [LLHD] Add canonicalizer for ProcessOp by @maerhart in #8221
• Bump LLVM to 289b17635958d986b74683c932df6b1d12f37b70. by @mikeurbach in #8225
• [RTG] Add the PyRTG frontend by @maerhart in #8187
• [Verif] Add simulation op by @fabianschuiki in #8224
• [LLHD] Don't implement BranchOpInterface for WaitOp by @maerhart in #8241

New Contributors

• @likeamahoney made their first contribution in #8213

Full Changelog: firtool-1.105.0...firtool-1.106.0

firtool-1.105.0

What's Changed

• [RTG] Populate pipeline with new passes by @maerhart in #8139
• [RTG] Add label visibility API by @maerhart in #8140
• [RTGTest] Add integer register type API by @maerhart in #8141
• [RTGTest] Add the last remaining ops for RV32I by @maerhart in #8142
• [HW] Add array_concat of one element folder by @maerhart in #8181
• [MooreToCore] Convert SCF ops inside llhd.process to CF by @maerhart in #8175
• [MooreToCore] Don't insert wait event checks if all detects are AnyChange by @maerhart in #8178
• [MooreToCore] Properly handle OOB accesses of moore.extract by @maerhart in #8182
• [NFC][Verif] Clarify symbolic_value semantics by @TaoBi22 in #8177
• [circt-verilog] Fix negative Rest timing by @maerhart in #8174
• [circt-verilog] Add LLHD lowering pipeline by @maerhart in #8179
• [MooreToCore] Branch to resume block instead of wait block by @maerhart in #8184
• [CombToAIG] Add support for div/mod operations by @uenoku in #8130
• [ESI Runtime] Pluggable channel engines by @teqdruid in #8167
• [MooreToCore] Add nested moore.conditional support by @AndreyVV-100 in #8125
• [LLHD] Removing llhd-sim tests by @teqdruid in #8036
• [RTG] Custom parser/printer for sequence op and type for sequence families by @maerhart in #8146
• [RTG] Separate operation for sequence randomization and randomized sequence type by @maerhart in #8147
• [RTG] Support partial sequence substitutions by @maerhart in #8148
• [RTG] Add operation to get a random number within a range by @maerhart in #8149
• [FIRRTL] FART: allow modules to be in multiple domains at once by @youngar in #8172
• [ESI][BSP] Service implementation via selectable engine by @teqdruid in #8186
• [FIRRTL] Disallow reading from property ports by @youngar in #8191
• [ImportVerilog] Fix bit slicing into variables declared with offset by @maerhart in #8190
• [FIRRTL] Add require and ensure intrinsics by @fabianschuiki in #8154
• [LLHD][TCM] Ignore processes with CFG loops within a TR by @maerhart in #8196
• [FIRRTL] Add contract declaration by @fabianschuiki in #8156
• [FIRRTL] Fix hasDontTouch crash on non-module block args by @fabianschuiki in #8157
• [FIRRTL][IMDCE] Support operations with blocks by @fabianschuiki in #8158
• [ImportVerilog]Support real math functions. by @hailongSun2000 in #8192
• [ESI][BSP] Emit engine records by @teqdruid in #8204
• [ESI][Runtime] Throw unknown engine error lazily by @teqdruid in #8205
• [FIRRTL] Add optional yaml parameter to view intrinsic, op by @dtzSiFive in #8203

Full Changelog: firtool-1.104.0...firtool-1.105.0

firtool-1.104.0

What's Changed

• [SCFToCalyx] Remove init_xxx_instance in BuildCallInstance by @jiahanxie353 in #8127
• [FIRRTL][IMCP] Overdefine ports of modules with unknown symbol uses by @fabianschuiki in #8115
• [SCFToCalyx] Lower floating point comparison logic fix by @jiahanxie353 in #8131
• [MemoryBanking] Adjust default dimension by @jiahanxie353 in #8132
• [MemoryBanking] Operation-granularity banking configurations by attaching attributes by @jiahanxie353 in #8133
• Add passes to strip OM and Emit dialect ops by @fabianschuiki in #8121
• [ESI][BSP] Gearboxing the hostmem write path by @teqdruid in #8136
• [ESI][BSP] Multiplexing hostmem write clients by @teqdruid in #8137
• [Verif] LowerContractsPass by @leonardt in #7870
• [ESI][BSP] Adding byte enables to cosim hostmem by @teqdruid in #8138
• [ExportVerilog] Treat verif.contract as no-op by @fabianschuiki in #8143
• [ESI][XRT BSP] Host memory writes by @teqdruid in #8152
• [Verif] Add ContractOp to Visitor by @fabianschuiki in #8155
• [Verif] Add StripContracts pass by @fabianschuiki in #8144
• [RTGTest] Add representation for immediates by @maerhart in #8053
• [RTGTest] Add a few instructions by @maerhart in #8056
• [RTG] Add ISA assembly emission pass by @maerhart in #8057
• [RTG] Add simple linear scan register allocation pass by @maerhart in #8058
• [RTGTest] Add dialect materializer by @maerhart in #8063
• [RTG][Elaboration] Do not internalize primitive values by @maerhart in #7997
• [RTG] More convenient InstructionOpInterface methods by @maerhart in #8100
• [RTG][Elaboration] Support fixed and virtual registers by @maerhart in #8101
• [RTGTest] Add branch instructions by @maerhart in #8105
• [docs] Add circt-bmc usage information to FormalVerification.md by @TaoBi22 in #8165
• [RTG][EmitISA] Support labels by @maerhart in #8106
• [RTG][Elaboration] Support labels by @maerhart in #8107
• [RTGTest] Add some arithmetic instructions by @maerhart in #8117
• [RTGTest] Add store instructions by @maerhart in #8118
• [FIRRTL] LowerXMR: process all modules by @youngar in #8168
• [LLHD] Move maxPrimitives check before initializing the 'dontCare' table by @maerhart in #8171
• Add Randomization Logic to Generated Memories by @seldridge in #8170

Full Changelog: firtool-1.103.0...firtool-1.104.0

firtool-1.103.0

What's Changed

• [ESI] Snoop op by @teqdruid in #8096
• [ESI] BSP: variable sized reads and gearboxing read responses by @teqdruid in #8095
• [FIRRTL] LowerLayers: Update innerrefs in extracted verbatim's by @dtzSiFive in #8094
• [ESI] BSP: implement hostmem read path arbiter by @teqdruid in #8102
• [FIRRTL] GrandCentral: Support firrtl.view by @dtzSiFive in #8092
• [SCFToCalyx] Canonicalize scf::if at the end of BuildParGroup by @jiahanxie353 in #8103
• [OM] Preserve non-OM operations in OM LinkModules by @uenoku in #8109
• [Python] Switch CIRCT Python extension and dialects to nanobind. by @mikeurbach in #8110
• Bump LLVM to aa580c2ec5eb4217c945a47a561181be7e7b1032. by @mikeurbach in #8108
• [FIRRTL][Inliner] Don't remove modules with symbol uses by @fabianschuiki in #8113
• [FIRRTL][IMDCE] Don't remove modules with symbol uses by @fabianschuiki in #8114
• [Pipeline] Make reset signal optional by @mortbopet in #8104
• [FIRRTL] Move GC after AssignOutputDirs. by @dtzSiFive in #8112
• [Pass] Remove unnecessary OperationPassmlir::ModuleOp by @uenoku in #8116
• [README] Fix badge link by @uenoku in #8124
• [FIRRTL] GrandCentral: set iface output_file based on parent. by @dtzSiFive in #8120
• [HW] Enable parametric polymorphism for module parameters by @bubblepipe42 in #8040
• [RTGTest] Improved register representation by @maerhart in #8052
• [ESI][Runtime] XRT support for host memory access by @teqdruid in #8122
• [MemoryBanking] Prevent name clashing when two memref::global ops have the same shape by @jiahanxie353 in #8119
• [ESI][XRT] Hostmem service: read side for XRT platform by @teqdruid in #8123
• [FIRRTL] Add circt_view intrinsic lowering to firrtl.view by @dtzSiFive in #8083

New Contributors

• @bubblepipe42 made their first contribution in #8040

Full Changelog: firtool-1.102.0...firtool-1.103.0

firtool-1.102.0

What's Changed

• Bump LLVM to ebc7efbab5c58b46f7215d63be6d0208cb588192. by @mikeurbach in #8089
• [HW][circt-synth] Implement AggregateToComb pass and add to circt-synth pipeline by @uenoku in #8068
• [SCFToCalyx] Wrap blocks with scf::ExecuteRegion when creating the new scf::Parallel by @jiahanxie353 in #8098
• [Kanagawa] Remove %this by @mortbopet in #8097
• [RTG][Elaboration] Move ConstantLike check after TypeSwitch for better performance by @maerhart in #7998
• [ExtractInstances] Append original instance name to path in metadata by @prithayan in #7872

Full Changelog: firtool-1.101.0...firtool-1.102.0

firtool-1.101.0

What's Changed

• [SMT] Parse SMT bitvector width as signed by @TaoBi22 in #8042
• [SMT] Add bv2int op by @TaoBi22 in #8049
• [MemoryBanking] Support memory banking forGetGlobalOp by @jiahanxie353 in #8047
• [FIRRTL][CAPI] add LayerConvention Enum and Attr by @sequencer in #8073
• [SCFToCalyx] Re-initialize IRMapping at the start of each loop by @jiahanxie353 in #8075
• [SMT][python] enable python bindings by @makslevental in #8071
• [FIRRTL] Reuse XMRRefOps in LowerXMR by @seldridge in #8066
• [Verif] disambiguate ctor by @makslevental in #8076
• [CMake] enable install C API objects by @makslevental in #8077
• [CAPI] disambiguate mlirRegisterConversionPasses by @makslevental in #8072
• [SCFToCalyx] Insert scf::reduce op at the end of the newly create scf::par op by @jiahanxie353 in #8080
• [SCFToCalyx] Insert terminator at the end of the newly created func op by @jiahanxie353 in #8081
• [ESI] Add hostmem write support to cosim by @teqdruid in #8059
• [CombToAIG] Add shl/shru/shrs lowering by @uenoku in #8067
• [RTG][Elaboration] Support sequences by @maerhart in #7969
• [RTG][Elaboration] Add support for 'index.add' and 'index.cmp' by @maerhart in #7978
• [FIRRTL] Intrinsics: Add checkAndConvert, anchor vtable. by @dtzSiFive in #8082
• [SCFToCalyx] Lower scf.if op when it yields nothing by @jiahanxie353 in #8079
• [SwitchToIf] Empty yielded result by @jiahanxie353 in #8087
• [LowerFormalToHW] Avoid applyPatternsGreedily, NFCI by @uenoku in #8088
• [circt-test] Allow tests to filter according to test runners by @fabianschuiki in #8084
• [RTG] Add InstructionOpInterface by @maerhart in #7979
• [FIRRTL] Add View Intrinsic by @seldridge in #8026
• [RTG] Add context resource attribute interface by @maerhart in #8034
• [CI/CD] Update upload-artifacts and download-artifcats. by @mikeurbach in #8090
• [CI] Enable Windows builds for PRs by @SpriteOvO in #8085
• [ImportVerilog] Add foreach statement support. by @chenbo-again in #8017
• [RTG][Elaboration] Add support for 'scf.if' and 'scf.for' by @maerhart in #7986

Full Changelog: firtool-1.100.0...firtool-1.101.0

firtool-1.100.0

What's Changed

• [CombToAIG] Add a pattern for mul by @uenoku in #8015
• [Comb] Don't try to canonicalize muxes indefinitely by @maerhart in #8023
• [PyCDE][Python] Fixing leaks reported by nanobind by @teqdruid in #8029
• [ESI/PyCDE] Updating XRT BSP to use ChannelMMIO by @teqdruid in #8025
• [HWToBTOR2] Fix incorrect le/ge predicate name emission by @TaoBi22 in #8028
• [MemoryBanking] Rename memory bank invalid test by @jiahanxie353 in #8032
• [RTGTest] Add some registers by @maerhart in #7924
• [VerifToSMT] Fix incorrect loop region result indexing by @TaoBi22 in #8006
• [CombToAIG] Lower comb.icmp by @uenoku in #8016
• [FIRRTL] Use PRINTF_FD macro instead of 0x80000002 as printf fd by @Clo91eaf in #7983
• Use MLIR python detection environment by @cbalint13 in #8037
• [SMT] Add int2bv operation by @TaoBi22 in #8041
• Revert "Use MLIR python detection environment (#8037)" by @mikeurbach in #8038
• [PyCDE] Improving support for Any type by @teqdruid in #8044
• [PyCDE/ESI] Add ESI hostmem service write API by @teqdruid in #8045
• [MemoryBanking] Support multi-dimension memory banking by @jiahanxie353 in #8033
• [MemoryBanking] Add a new field to keep track values to be erased by @jiahanxie353 in #8039
• [circt-test] Keep a list of available test runners by @fabianschuiki in #8046
• [Python] Update wheels we build in CI/CD. by @mikeurbach in #8051
• Bump LLVM to 560b72c0408a8f7e4340a1d4197b164a14cd30b0. by @mikeurbach in #8043
• [LoopScheduleToCalyx] Lower pipeline register to register writes. by @cgyurgyik in #8048
• [LoopScheduleToCalyx] deduplicate groups within a ParOp. by @cgyurgyik in #8055

New Contributors

• @Clo91eaf made their first contribution in #7983
• @cbalint13 made their first contribution in #8037

Full Changelog: firtool-1.99.2...firtool-1.100.0

firtool-1.99.2

What's Changed

• [Seq] Fix FIFO lowering to correct depth and pointer increments by @teqdruid in #8003
• [ESI] FIFO with ESI channels by @teqdruid in #8004
• [LowerToBMC] Topologically sort module body before inlining to BMC op by @TaoBi22 in #8007
• [PyCDE] Update build flow by @teqdruid in #8008
• [ESI] FIFO: support valid/ready on inputs and outputs by @teqdruid in #8009
• [PyCDE] Add fork, join, and merge channel functions by @teqdruid in #8011
• [Comb] delete slow canonicalizer by @youngar in #8014

Full Changelog: firtool-1.99.1...firtool-1.99.2