Firtool Release 1.74.0

What's Changed

• [FIRRTL] Gather intrinsic lowering via dialect interface. by @dtzSiFive in #6923
• [FIRRTL] no back-prop for width of mux selectors, support narrower by @dtzSiFive in #6917
• Update annotation handling to fix partial field reset behavior by @adkian-sifive in #6912
• [Arc] Fix segfault in SplitLoops by @Moxinilian in #6928
• [HWToBTOR2] Deduce resets from (Fir)RegOps by @TaoBi22 in #6918
• Bump llvm by @azidar in #6932
• [FIRRTL] Disambiguate paths when possible in ResolvePaths. by @mikeurbach in #6937
• [SMT] Added weight attribute support for ExportSMTLIB by @luisacicolini in #6920
• [SMT] Add lowering to LLVM IR by @maerhart in #6902
• [SMTToLLVM] Add support for most expressions by @maerhart in #6905
• [circt-lec] Port to SMT dialect based compiler pipeline by @maerhart in #6908
• [ImportVerilog] Add replicate and extract operations. by @hailongSun2000 in #6906
• [ImportVerilog] Add case statement. by @angelzzzzz in #6929
• [ImportVerilog] Fix the types mismatch for variable declarations. by @hailongSun2000 in #6907
• [Moore] Introduce a new operation - netOp for net declaration by @cepheus69 in #6884
• [FIRRTL][CAPI] Add function for getting mask type by @SpriteOvO in #6944
• [HandshakeToDC] Fix constant unit-rate op lowering by @mortbopet in #6942
• [Comb] Remove more idempotent operands by @hovind in #6903
• [MooreToCore] Lower moore operators into comb or hw. by @hailongSun2000 in #6940
• [Scheduling] computeStartTimesInCycle: clear before recomputation by @7FM in #6951
• [FIRRTL] Don't fail compilation when Dedup group annotation is on EICG_wrapper by @uenoku in #6955

New Contributors

• @luisacicolini made their first contribution in #6920
• @hailongSun2000 made their first contribution in #6906
• @angelzzzzz made their first contribution in #6929

Full Changelog: firtool-1.73.0...firtool-1.74.0

firtool-1.73.0

What's Changed

• [Pipeline] Remove Pure trait from Pipeline operations by @mortbopet in #6888
• [Ibis] Introduce 'ibis.design' by @teqdruid in #6835
• [Ibis] fix invalid std::optional dereferencing by @mortbopet in #6895
• Bump LLVM to latest by @seldridge in #6894
• [FIRRTL] Fixup visit ops miscategorized. by @dtzSiFive in #6896
• [FIRRTL][NFC] Remove dead signal driving annos. by @dtzSiFive in #6898
• [FIRRTL] Drop support for long-unused subcircuit annotations. by @dtzSiFive in #6899
• [SMT] Minor width related fixes for BitVectorAttr by @fzi-hielscher in #6900
• [LowerToHW] Wrap signed operands of PrintFOp in sv $signed() by @ubfx in #6887
• [FIRRTL][CAPI] Allow constructing integers larger than 64 bits by @SpriteOvO in #6893
• [FIRRTL] Use a flag to implement scalarization of internal modules. … by @darthscsi in #6901
• [FIRRTL] Generic intrinsic parsing/emitter support by @dtzSiFive in #6897
• [CreateSiFiveMetadata] Generate firrtl.class instead of om.class by @prithayan in #6736
• [LowerFirReg] Reimplement the mux reachability analysis by @prithayan in #6709
• [FIRRTL] LowerIntrinsics: rewrite to lower generic ops. by @dtzSiFive in #6877
• [FIRRTL][LowerIntmodules] Add stats, preserve if nothing changed. by @dtzSiFive in #6910
• [Ibis] Divorce port name (hints) from port symbol names by @mortbopet in #6909
• [LowerFirReg] Reimplement the mux reachability analysis by @prithayan in #6914
• llvm: bump by @dtzSiFive in #6915
• [FIRRTL][NFC] Use underscores in documentation. by @dtzSiFive in #6860

Full Changelog: firtool-1.72.0...firtool-1.73.0

Firtool Release 1.72.0

I messed up https://github.com/llvm/circt/releases/tag/firtool-1.71.0, sorry! This contains the correct (and many repeated) commits.

What's Changed

• [NFC] Move 'using namespace' out of headers. by @fzi-hielscher in #6844
• [FSM][Emit] Convert the FSMToSV pass to use emit ops by @nandor in #6828
• [Emit][Seq] Emit random init headers using fragments by @nandor in #6826
• [HW][IST] Verify simple inner-ref-user ops sequentially, perf fix. by @dtzSiFive in #6850
• Fix a few FileCheck directive typos. by @dtzSiFive in #6853
• [FIRRTL][NFC] Move xmr.ref and xmr.deref into expressions. by @dtzSiFive in #6852
• [circt-lec] Add ConstructLEC pass by @maerhart in #6833
• StripDebugInfoWithPred: Fix parallelization perf issue. by @dtzSiFive in #6851
• [ImportVerilog] Add if and loop statements by @fabianschuiki in #6831
• [FIRRTL] Remove support for circt.Intrinsic annotation. by @dtzSiFive in #6857
• [FIRRTL] Make "intrinsic" name of intmodule mandatory. by @dtzSiFive in #6858
• [Docs] Extend formal verification documentation by @maerhart in #6854
• [Seq] Erase memories with no read ports by @nandor in #6861
• [ImportVerilog] Add assign and pre/post increment/decrement expressions by @fabianschuiki in #6859
• [SMT] Add quantifier operations by @maerhart in #6842
• [SMT] Add function application operation, function and uninterpreted sort types by @maerhart in #6847
• [SV][Verif] Extract verif ops in SVExtractTestCode by @seldridge in #6865
• [NFCI] Declare common attributes for fmodule* by @darthscsi in #6868
• [FIRRTL] Cache a symbol table instead of doing linear lookups every instance. by @darthscsi in #6871
• [LowerToHW] Set fragments outside the parallel region by @nandor in #6872
• [SMT] Add SMT-LIB export translation by @maerhart in #6870
• [FIRRTL] Add generic intrinsic op. by @dtzSiFive in #6874
• [FIRRTL] Add LowerIntmodules pass. by @dtzSiFive in #6876
• [FIRRTL] Change Port Direction attribute from an APInt to a DenseArray. by @darthscsi in #6875
• [FIRRTL] Add intrinsic for UNR only assume by @uenoku in #6867
• [FIRRTL] Add CreateCompanionAssume pass; Decouple UNROnlyAssume generation from AssertOp lowering by @uenoku in #6863
• [NFC] Make fewer copies of directions by @darthscsi in #6879
• [Docs] GettingStarted: Fix images and LLVM/MLIR contributing guide by @ubfx in #6873
• [FIRRTL] Deprecate AssertAssume intrinsic and rename it to Assert by @uenoku in #6878
• [Docs] Correct a typo in circt-lec/README.md by @felixonmars in #6849
• [FIRRTL] Treat blackboxes in layers as "testbench" by @seldridge in #6881
• [SeqToSV] Fix the ordering of the memory/register random init fragments by @nandor in #6883
• [NFC] Massive Export Verilog Speedup by @darthscsi in #6886
• [LowerToHW] Emission Option for verification flavors by @uenoku in #6885
• [FIRRTL] Expose clock dividers as a FIRRTL intrinsic by @nandor in #6890
• [CFToHandshake] Move Transforms dependency to implementation by @mortbopet in #6889
• [NFC] Cache common lookups in ModuleType by @darthscsi in #6892

New Contributors

• @ubfx made their first contribution in #6873
• @felixonmars made their first contribution in #6849

Full Changelog: firtool-1.70.0...firtool-1.72.0

Firtool Release 1.71.0

What's Changed

• [NFC] Move 'using namespace' out of headers. by @fzi-hielscher in #6844
• [FSM][Emit] Convert the FSMToSV pass to use emit ops by @nandor in #6828
• [Emit][Seq] Emit random init headers using fragments by @nandor in #6826
• [HW][IST] Verify simple inner-ref-user ops sequentially, perf fix. by @dtzSiFive in #6850
• Fix a few FileCheck directive typos. by @dtzSiFive in #6853
• [FIRRTL][NFC] Move xmr.ref and xmr.deref into expressions. by @dtzSiFive in #6852
• [circt-lec] Add ConstructLEC pass by @maerhart in #6833
• StripDebugInfoWithPred: Fix parallelization perf issue. by @dtzSiFive in #6851
• [ImportVerilog] Add if and loop statements by @fabianschuiki in #6831
• [FIRRTL] Remove support for circt.Intrinsic annotation. by @dtzSiFive in #6857
• [FIRRTL] Make "intrinsic" name of intmodule mandatory. by @dtzSiFive in #6858
• [Docs] Extend formal verification documentation by @maerhart in #6854
• [Seq] Erase memories with no read ports by @nandor in #6861
• [ImportVerilog] Add assign and pre/post increment/decrement expressions by @fabianschuiki in #6859
• [SMT] Add quantifier operations by @maerhart in #6842
• [SMT] Add function application operation, function and uninterpreted sort types by @maerhart in #6847
• [SV][Verif] Extract verif ops in SVExtractTestCode by @seldridge in #6865

Full Changelog: firtool-1.70.0...firtool-1.71.0

firtool-1.70.0

What's Changed

• [SMT] Add declare_const, assert, solver, and check operations by @maerhart in #6806
• [SMT] Add comparison operations by @maerhart in #6807
• [SMT] Add concat, extract, repeat operations by @maerhart in #6813
• [SMT] Add boolean logic operations by @maerhart in #6814
• [SMT] Add HWToSMT and CombToSMT conversion passes by @maerhart in #6815
• [SMT] Add constant boolean operation by @maerhart in #6825
• [Verif] Add LEC operation by @maerhart in #6832
• [CombToSMT] Add parity op support by @maerhart in #6837
• [SMT] Add integer constant and arithmetic operations by @maerhart in #6838
• [arcilator] Introduce integrated JIT for simulation execution by @Moxinilian in #6783
• [Emit] Copy fragments into modules created by ExtractTestCode by @nandor in #6843

Full Changelog: firtool-1.69.0...firtool-1.70.0

Firtool Release 1.69.0

What's Changed

• [FIRRTL] Reject ref statements in 4.0.0+. by @dtzSiFive in #6738
• [OM] Extend APSInts as necessary before performing arithmetic. by @mikeurbach in #6786
• [OM] Add C API and Python bindings for IntegerAttr to string. by @mikeurbach in #6787
• [CMake] Add CMake targets to install all CIRCT libraries. by @mikeurbach in #6798
• [FIRRTL] Fix sign bit truncation in constant parser by @fabianschuiki in #6794
• [FIRRTL][CheckCombLoops] don't crash on force+rwprobeop, workaround. by @dtzSiFive in #6821
• [FIRRTL] Support alternative base paths in LowerClasses. by @mikeurbach in #6817
• [Emit] Group file header ops into emit.fragment by @nandor in #6789
• [FIRRTL][LowerAnnotations] Fix non-probe type compat check. by @dtzSiFive in #6822
• [ExportVerilog] Spill LTL operands used in event control if not allowed. by @dtzSiFive in #6829
• [InferRW] Remove dependence of write-mode on enable for memory by @prithayan in #6818
• [InferReadWrite] Add heuristic to infer unmasked memory by @prithayan in #6790
• [FIRParser] Do not swallow stop ops when parsing FIR by @nandor in #6834
• [InferReadWrite] Set builder insertion point to ensure dominance by @prithayan in #6836

Full Changelog: firtool-1.68.0...firtool-1.69.0

firtool-1.67.1

Full Changelog: firtool-1.67.0...firtool-1.67.1

firtool-1.68.0

What's Changed

• [ImportVerilog] Add assignment statements by @fabianschuiki in #6773
• [WireDFT] Remove WireDFT by @nandor in #6761
• [SV] Use a symbol in macro identifiers by @nandor in #6777
• [Sim] Emit a SYNTHESIS macro declaration if needed by @nandor in #6778
• [SV] Verify macro reference symbols by @nandor in #6780
• [FIRRTL] Handle reference ports when Classes dedup. by @mikeurbach in #6770
• LLVM bump by @prithayan in #6782
• [Seq] Allow presets for more types on firreg by @nandor in #6781
• [OM] Add C API and Python bindings for EvaluatorValue::Reference. by @mikeurbach in #6785
• Bump LLVM to 1e828f838cc0f15074f3dbbb04929c06ef0c9729. by @mikeurbach in #6784
• [FIRTOOL] Move LowerIntrinsic to preprocess by @uenoku in #6796

Full Changelog: firtool-1.67.0...firtool-1.68.0

firtool-1.67.0

What's Changed

• [LLVM] Bump by @nandor in #6718
• [FIRRTL] Update HierPathOps in LowerLayers by @seldridge in #6721
• [ESI][Runtime] Use std::future in channel reads and func calls by @teqdruid in #6723
• [FIRRTL] Add integer addition conversion to LowerClasses. by @mikeurbach in #6710
• [OM] Support integer binary arithmetic in the Evaluator. by @mikeurbach in #6711
• [FIRTOOL] More sane chisel interface directory handling by @darthscsi in #6687
• [FIRRTL] Prevent divison by zero in CreateSiFiveMetadata by @fzi-hielscher in #6726
• [ImportVerilog] Add translation, run Slang compilation by @fabianschuiki in #6708
• [FIRRTL] Support PropertyType in emitConnect. by @mikeurbach in #6734
• [PyCDE] Wrappers for Ibis classes by @teqdruid in #6631
• [FIRRTL] Check unknown width and reset rules during parsing 4.0.0. by @dtzSiFive in #6731
• [Sim] Introduce wrappers on top of sv.finish/sv.fatal by @nandor in #6737
• [FIRRTL][CAPI] Add function for importing annotations by @SpriteOvO in #6730
• [Emit] Organize output files using the emit dialect by @nandor in #6727
• [ExportVerilog][Emit] Export emitted files by @nandor in #6728
• [Emit] Emit black boxes through emit ops by @nandor in #6729
• [ImportVerilog] Convert empty modules and instances by @fabianschuiki in #6743
• [FIRRTL][LowerLayers] Clean up names of artifacts generated by layers by @rwy7 in #6733
• [Ibis] Split ContainerOp in two by @teqdruid in #6739
• [Emit] Emit SV ops nested in a file by @nandor in #6744
• [FIRRTL][FIRParser] Enforce 4.0.0 main module must be public. by @dtzSiFive in #6747
• [Emit] Use FileOp to emit metadata by @nandor in #6746
• [MSFT][Emit] Replace output_file with an emit::File by @nandor in #6751
• [Emit] Convert the ExtractInstances pass to use file ops by @nandor in #6756
• [ExtractInstances] Fix Windows CI by @nandor in #6758
• [HGLDD] Fix instance output port emission by @fabianschuiki in #6750
• [HGLDD] Uniquify object names during emission by @fabianschuiki in #6753
• [HW to BTOR2] Add support for initial values by @dobios in #6754
• [ImportVerilog] Add type conversion and basic variables by @fabianschuiki in #6755
• [ESI][Runtime] Building wheels by @teqdruid in #6759
• [HW] Remove the file list attribute from HW by @nandor in #6757
• [ESI][Runtime] Build and publish wheels by @teqdruid in #6763
• [FIRRTL] Put layer collateral in testbench dir by @seldridge in #6741
• [ESI] Move entirely over to the runtime for testing by @teqdruid in #6764
• [Emit] Introduce emit.ref to pull ops into file bodies by @nandor in #6762
• [Calyx] Switch sequential memories to be true single port memories by @andrewb1999 in #6765
• [ImportVerilog] Convert initial/always/final procedures by @fabianschuiki in #6766
• [Calyx] Fix memory import locations by @andrewb1999 in #6769
• [arcilator] Introduce simulation orchestration subdialect by @Moxinilian in #6695
• [FIRRTL] Use the class map in ObjectOp parser. by @mikeurbach in #6771
• [capi][python] Add Emit Dialect by @seldridge in #6774

Full Changelog: firtool-1.66.0...firtool-1.67.0

firtool-1.66.0

What's Changed

• [HW] Lower hw.instance_choice to SV by @nandor in #6624
• [ESI][Runtime] Convert Type& to Type* by @teqdruid in #6644
• [ESI][Runtime][NFC] Move requestChannelsFor into accelerator connection by @teqdruid in #6646
• [ESI][Runtime] Add the notion of a Context by @teqdruid in #6647
• [ESI][Runtime][NFC] Switch from ptr,size to MessageData by @teqdruid in #6648
• Fix some issues in the LayerBlockOp verifier by @rwy7 in #6654
• [FIRRTL] Use set-based logic to test for layer compatibility by @rwy7 in #6643
• [FIRRTL] Intrinsics: Fix mistakenly preserved analyses. by @dtzSiFive in #6666
• [OM] Remove Symbol trait from ClassFieldLikes. by @mikeurbach in #6665
• [Calyx] Make ControlOp a SymbolTable. by @mikeurbach in #6670
• [IMCP] Fix a race condition regarding aggregate preservation by @uenoku in #6671
• Track instance layers by @rwy7 in #6663
• [CI] Add statically linked CIRCT full build to ReleaseArtifact CI by @uenoku in #6544
• [FIRRTL] chisel_{assert_assume,assume,cover,ifelsefatal} intrinsics. by @dtzSiFive in #6664
• [ImportVerilog] Add import options and Verilog preprocessing by @fabianschuiki in #6632
• Allow propassign under layerblocks by @rwy7 in #6656
• [Seq] Remove Symbol trait from HLMemOp. by @mikeurbach in #6676
• [ESI][Runtime] Adding support for FuncService by @teqdruid in #6673
• [FIRRTL] InferResets: verify that FART annotation is on async resets by @youngar in #6674
• [FSM] Remove Symbol trait from InstanceOp and HWInstanceOp. by @mikeurbach in #6675
• [FIRRTL][LowerXMR] Use FIRRTL 4.0 ref ABI. by @dtzSiFive in #6677
• Tree-wide test fixes for FileCheck directive typos by @dtzSiFive in #6679
• [LowerIntrinsics] Accept EICG_wrapper without test_en, reject annos by @fabianschuiki in #6678
• [WireDFT] Disable the pass by default by @nandor in #6684
• [LowerToHW] Fix shr(0-bit, n) lowering by @seldridge in #6683
• [ImportVerilog] Fix single unit preprocessor option by @fabianschuiki in #6682
• [arcilator] Remove PrintStateInfo pass by @Moxinilian in #6529
• LLVM bump by @darthscsi in #6662
• Make circt-verilog available to integration tests. by @dtzSiFive in #6685
• [LowerClasses] Lower classes that instantiate properties. by @mikeurbach in #6688
• [FIRRTL] Add layer-associated Probes to LowerLayers pass by @seldridge in #6554
• [ExportVerilog] Fix crash on sv.reg with initial value by @fzi-hielscher in #6689
• [HW] Encode the option group name in instance choice ops by @nandor in #6645
• [HW] HWModule: store input port locations only on block args by @youngar in #6642
• [FIRRTL] Add parser version APIs that accept an SMLoc, NFC. by @mikeurbach in #6692
• [FIRRTL] Provide a way to override inferReturnTypes in FIRRTLExprOp. by @mikeurbach in #6697
• [FIRRTL] Add integer addition property op. by @mikeurbach in #6691
• [OM] Add rationale for expressions. by @mikeurbach in #6702
• [OM] Add OpInterface for IntegerBinaryArithmeticOp. by @mikeurbach in #6703
• [PyCDE] Refactor Input/Output ports to extend property by @teqdruid in #6700
• [FIRRTL] Add integer addition parser support. by @mikeurbach in #6701
• [CMake] Make ImportVerilog compile-time depend on slang by @fzi-hielscher in #6707
• [FIRRTL][Lower-Layers] do not capture uses multiple times by @rwy7 in #6699
• [FIRRTL] Change min width of shr for UInt to 0 by @jackkoenig in #6698
• [FIRRTL] Use untyped propassign source accessor in LowerClasses. by @mikeurbach in #6690
• [OM] Add integer addition op. by @mikeurbach in #6704

New Contributors

• @Moxinilian made their first contribution in #6529

Full Changelog: firtool-1.65.0...firtool-1.66.0