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Pull requests list

[MLIR][ODS] Fix properties tablegen wrapper to allow ADL lookup for hash_value mlir:core MLIR Core Infrastructure mlir:ods mlir
#141023 opened May 22, 2025 by joker-eph Loading…
2
Revert "[X86] Improve @gotpcrel on local symbol tests" backend:X86 LTO Link time optimization (regular/full LTO or ThinLTO) mc Machine (object) code
#141021 opened May 22, 2025 by mariusz-sikora-at-amd Loading…
3
[mlir][math] Fix intrinsic conversions to LLVM for 0D-vector types mlir
#141020 opened May 22, 2025 by AGindinson Loading…
3
[MLIR] Add bufferization state class to OneShotBufferization pass mlir:arith mlir:bufferization Bufferization infrastructure mlir:cf mlir:linalg mlir:mlprogram mlir:scf mlir:shape mlir:sparse Sparse compiler in MLIR mlir:tensor mlir:vector mlir:vectorops mlir
#141019 opened May 22, 2025 by mscuttari Loading…
5
[mlir] Explain required attrs for CallOpInterface in Toy (NFC) mlir
#141018 opened May 22, 2025 by jjvraw Loading…
2
[RISCV] add Double Trap extensions requires Zicsr backend:RISC-V mc Machine (object) code
#141016 opened May 22, 2025 by jerryzj Loading…
1
[InstCombine] Generalize ignoreSignBitOfZero/NaN to handle more cases llvm:instcombine llvm:transforms
#141015 opened May 22, 2025 by dtcxzyw Loading…
1
[libc++] Temporarily disable the lldb tests
#141014 opened May 22, 2025 by philnik777 • Draft
[InstCombine] Propagate FMF from select instead of fcmp
#141010 opened May 22, 2025 by dtcxzyw • Draft
1
[RISCV] Implement base scheduling model for andes 45 series processor. backend:RISC-V
#141008 opened May 22, 2025 by tclin914 Loading…
1
[mlir] Optimize const values AffineMap::compose mlir:core MLIR Core Infrastructure mlir
#141005 opened May 22, 2025 by qazwsxedcrfvtg14 Loading…
1
release/20.x: [clang-format] Fix the indent of StartOfName after Attr… clang-format
#141004 opened May 22, 2025 by owenca Loading… LLVM 20.X Release
1
release/20.x: [clang-format] Handle raw string literals containing JSON code (#140666) clang-format
#141002 opened May 22, 2025 by llvmbot Loading… LLVM 20.X Release
2
Check for immediates using isLegalICmpImmediate backend:AArch64
#140999 opened May 22, 2025 by AZero13 Loading…
1
Fix a bug where using "thread backtrace unique" would switch you to lldb
#140993 opened May 22, 2025 by jimingham Loading…
2
[SelectionDAG][RISCV] Use VP_STORE to widen MSTORE in type legalization when possible. llvm:SelectionDAG SelectionDAGISel as well
#140991 opened May 22, 2025 by topperc Loading…
3
[clang] Use llvm::is_contained (NFC) clang:frontend Language frontend issues, e.g. anything involving "Sema" clang Clang issues not falling into any other category
#140985 opened May 22, 2025 by kazutakahirata Loading…
1
[HLSL] Diagnose overlapping resource bindings backend:DirectX llvm:analysis
#140982 opened May 22, 2025 by hekota Loading…
1
[HLSL] Move DXILResourceImplicitBinding pass closer to DXIL Resource Analysis backend:DirectX
#140981 opened May 22, 2025 by hekota Loading…
1
[mlir][Vector] Canonicalize empty vector.mask into vector.select mlir:vector mlir:vectorops mlir
#140976 opened May 22, 2025 by dcaballe Loading…
2
[lldb-dap] attempt to fix test_disassemble lldb
#140975 opened May 22, 2025 by eronnen Loading…
3
[RISCV][TTI] Implement getPartialReductionCost for the vqdotq cases backend:RISC-V llvm:transforms
#140974 opened May 22, 2025 by preames Loading…
2
[OpenACC][CIR] Add lowering for 'copy' array indexes clang Clang issues not falling into any other category ClangIR Anything related to the ClangIR project
#140971 opened May 21, 2025 by erichkeane Loading…
1
[TableGen] Add missing $ before the dag operator name tablegen
#140969 opened May 21, 2025 by anemet Loading…
1
[RISCV] Sort RISCVSystemOperands to match the RISC-V Privilege Specification. backend:RISC-V
#140967 opened May 21, 2025 by topperc Loading…
2
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