wishbone: A proposal to add Interconnect & related SoC building blocks

[ghost]

On this pull request, I propose new modules to introduce shared bus interconnection (as described in Section 8.2.3 of Wishbone B4) to this SoC building library and add some "shortcuts" for making such interconnection. This includes:

1. wishbone.bus.Arbiter: A module for bus arbitration. Originally (commits before 976cef4), my proposal would work only for standard handshake protocol without block reads/writes (usage of LOCK), pipelining (usage of STALL) or registed feedbacks (usage of CTI and BTE). As soon as I read @jfng's proposal (wishbone.bus: add Arbiter. #3), I realised the importance of including those features and I decided to adopt his design. Currently, the difference between our proposals is that mine separates the Round Robin arbitration/scheduling method from the Arbiter class, and makes it a standalone scheduler (scheduler.RoundRobin). See below for details.

2. scheduler.RoundRobin: A module to implement a Round Robin scheduler, which is mainly used for bus arbitration in wishbone.bus.Arbiter. Originally (commits before 976cef4), my proposal makes the scheduler ignore the initiator if it is not requesting for access to the interconnect shared bus. But @jfng's unit tests indicated that the arbiter should allow the masters to take turn to continue the transaction cycle with their targeted slave by locking while keeping its request, meaning the next master has to be granted access on every clock. Thus, I removed the If(~self.request[i]) from my code and made it work with the Arbiter adopted from @jfng.

3. wishbone.bus.InterconnectShared: A module for basic shared bus interconnection. For initialisation, it accepts a list of initiators (MASTERs) and a list of targets (SLAVEs), as well as the parameters for the shared bus (e.g. address & data widths, granularity), for the Arbiter on the MASTERs (e.g. arbitration method) and for the Decoder on the SLAVEs (e.g. address alignment). It instantiates the shared Wishbone bus, an Arbiter and a Decoder using these parameters, and connect the two to the shared bus.

4. wishbone.SRAM: A module for a simple readable or read/writable SRAM. Its memory read and write enable strobes follow the logics for READ and WRITE operations according to the Wishbone specification (Sections 3.2.1 and 3.2.3) respectively. Currently, no unit tests have been written for this module.

Better docstrings will be added ASAP. Thank you.

[codecov]

Codecov Report

Attention: Patch coverage is 78.36257% with 37 lines in your changes missing coverage. Please review.

Project coverage is 93.57%. Comparing base (3195de9) to head (46e3760).
Report is 7 commits behind head on master.

Files	Patch %	Lines
nmigen_soc/wishbone/sram.py	24.13%	22 Missing ⚠️
nmigen_soc/wishbone/bus.py	87.80%	7 Missing and 8 partials ⚠️

Additional details and impacted files

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- Coverage   100.00%   93.57%   -6.43%     
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  Files            4        6       +2     
  Lines          415      576     +161     
  Branches        91      134      +43     
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+ Hits           415      539     +124     
- Misses           0       29      +29     
- Partials         0        8       +8     

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