RTLCorrection

This document helps you to use this tool to correct an Buggy RTL design

Description

The input to the tool is the Verilog file of the buggy RTL design, the input C description of the design. The output will be the corrected RTL design that is similar to the buggy one.

Prequisities

1. You need to have LegUp (the open source high level synthesis tool) installed. It is recommended to download the whole virtual box OS image of the LegUp from http://legup.eecg.utoronto.ca/. After opening the OS containing the LegUp or intalling the LegUp on Linux, you can see the legup-4.0 in your home folder.
2. You need to have Yosys (the open source verilog compiler) installed. After successful intallation, you can see the yosys-master folder in your home folder.

Explaining the repo structure

We call the path of this README.md file the root. The other folders and pathes explained here are under the root.

1. genOCM folder: It contains the main developement files.

• mainNode.h and mainNode.cpp which implement the data structure for for both operations of the CDFG (OPS) and resources of the RTL (RPS).
• genOCM.h and genOCM.cpp that implement the class that provide all the functions needed for creating Processig Subgraphs (PS).
• BipartiteWeightedMatchingBinding.h and BipartiteWeightedMatchingBinding.cpp that are codes from LegUp itself, which are modified to fulfill our purposes.

2. editDotfil folder: It contains a simple code and binary with the aim of modifying the .dot file (the netlist outout of the Yosys tool).

3. Matching folder: It contains the matching algorithm and its binary based on hungrian matching method. This binary is used to find the final result.

4. other folder: It Contains small scripts to run the whole tool

5. runTest folder: It contains the python script that forcasts the CPU time of a mutation based method.

How to make the toolchain ready

Here we explain how to patch the LegUp and Yosys. Before making the patches, make copy of the legup-4.0 in the same path it is and rename it to original_legup. The original_legup will be used to create the buggy verilog files.

1. Patch the legUp:

• Replace the legup-4.0/examples/Makefile.common with other/makefile.common
• Replace the legup-4.0/examples/legup.tcl with other/legup.tcl
• Copy the whole content of other/genOCM folder to the legup-4.0/llvm/lib/Target/Verilog Answer yes to the question about replacing files.
• Run the make command to build the LegUp

2. Patch the Yosys:

• Replace the yosys-master/passes/cmds/show.cc with the other/show.cc
• run the make command to build to Yosys
• Copy the other/modify_verilog.sh to yosys-master
• Copy the other/syn.ys to yosys-master
• Copy the other/editfile to yosys-master
• Copy the other/creat_final_netlist.sh to yosys-master

How to correct an RTL design

Here we explain the way you can correct a buggy RTL design. We take the fir design as an example here.

1. To have buggy RTL design, we use original_legup to sythesize a buggy C code to a verilog code.

• cd to original_legup/examples/fir
• Make some changes in fir.c file to simulate the bug.
• open the command window and run the make command. The fir.v file will be created as buggy RTL.

2. Make the netlist from fir.v using Yosys

• Copy the original_legup/examples/fir/fir.v file to the yoysys-master

• cd to yoysys-master and and open terminal

• run the modify_verilog.sh with fir.v as argument; like modify_verilog.sh fir.v This command will modify the verilog file to be compatible to the verilog standard that is acceptable by yosys.

• Edit first line of the yosys-master/syn.ys to contain fir.v and last line to show memory_controller.

• Run the ./yosys syn.ys to create the hidden file named .yosys_show.dot. This is the netlist file for the memory_controller module of the fir.v. The RTL generated by LegUp ususally have main and memory_controller modules. If there was any RTL with more modules to should merge the functions of the input .c file to skip creating more modules.

• Rename the .yosys_show.dot file to memory_controller.dot.

• Edit last line of the yosys-master/syn.ys file to show main.

• Run the ./yosys syn.ys to create the hidden file named .yosys_show.dot.

• Rename the .yosys_show.dot to main.dot

• Run the creat_final_netlist.sh to create the final netlist files called main.dot, memory_controller.dot and total.dot

• Copy the 3 netlist files to the legup-4.0/examples/fir folder. They are inputs to the modified legUp that is our developed toolchain.

3. Create the corrected RTL: Now we have netlist of the buggy RTL as input to the fir folder of our modified LegUp.

• Change line 1128 of the legup-4.0/llvm/lib/Target/Verilog/genOCM.cpp to point to fir.ll
• cd to legup-4.0 and build it with make command to include the above change.
• cd to original_legup/examples/fir and run the make command to have the corrected fir.v.