README for Digital Logic Design (ECE 367) - Spring 1399-00

Repository Overview

This repository contains all the computer assignments (CA) for the Digital Logic Design course (ECE 367) offered by the Electrical and Computer Engineering Department during the Spring semester of 1399-00. The assignments are designed to provide hands-on experience in digital logic design, covering various topics such as combinational and sequential logic, state machines, and hardware description languages (HDLs).

Repository Structure

The repository is organized into separate directories for each computer assignment (CA). Each directory contains the relevant files, including Verilog code, testbenches, and any additional resources required for the assignment. Below is the structure of the repository:

├── AGholami98446-CA01-ECE894
├── AGholami98446-CA02-ECE894
├── AGholami98446-CA03-ECE894
├── AGholami98446-CA04-ECE894
├── AGholami98446-CA05-ECE894
├── AGholami98446-CA06-ECE894
└── README.md

Assignment Descriptions

1. CA01: Basic Switch and Gate Structures in SystemVerilog.
2. CA02: Basic RTL Packages.
3. CA03: RT Level Components, Iterative Logic, Synthesis.
4. CA04: Latches, flip-flops, and a little beyond.
5. CA05: State Machine Coding, Pre- and Post-Synthesis.
6. CA06: Hierarchical RTL Design.

How to Use This Repository

1. Clone the Repository: Start by cloning this repository to your local machine using the following command:

   git clone <repository-url>

2. Navigate to Assignment Directories: Each assignment is contained in its respective directory (e.g., AGholami98446-CA01-ECE894). Navigate to the directory of the assignment you are working on.
3. Run the Verilog Code: Use a Verilog simulator (e.g., ModelSim, Xilinx Vivado) to compile and simulate the Verilog code provided in each assignment. Modify the testbenches to verify the functionality of your designs.