Counter clockwise LED illumination

led_counterclockwise/.gitignore

@@ -0,0 +1 @@
+build

led_counterclockwise/Makefile

@@ -0,0 +1,33 @@
+# Project setup
+PROJ      = counterclock
+BUILD     = ./build
+DEVICE    = 1k
+#DEVICE    = 8k
+ifeq (8k,$(DEVICE))
+FOOTPRINT = ct256
+else
+FOOTPRINT = tq144
+endif
+
+# Files
+FILES = top.v
+
+.PHONY: all clean burn
+
+all:$(BUILD)/$(PROJ).bin
+
+$(BUILD)/$(PROJ).bin: $(FILES) Makefile
+	# if build folder doesn't exist, create it
+	mkdir -p $(BUILD)
+	# synthesize using Yosys
+	yosys -p "synth_ice40 -top top -blif $(BUILD)/$(PROJ).blif" $(FILES)
+	# Place and route using arachne
+	arachne-pnr -d $(DEVICE) -P $(FOOTPRINT) -o $(BUILD)/$(PROJ).asc -p pinmap_$(FOOTPRINT).pcf $(BUILD)/$(PROJ).blif
+	# Convert to bitstream using IcePack
+	icepack $(BUILD)/$(PROJ).asc $(BUILD)/$(PROJ).bin
+
+burn:   $(BUILD)/$(PROJ).bin
+	iceprog $<
+
+clean:
+	rm -f build/*

led_counterclockwise/README.md

@@ -0,0 +1,10 @@
+counter clockwise
+=================
+
+This example mostly aims at the HX1K circular layout of LEDs. It ships
+with a default clockwise rotation of blinking LEDs. The here presented
+firmware changes this to a counter clockwise orientation.
+
+The original is distributed with the arachne-pnr examples on 
+https://github.com/cseed/arachne-pnr/tree/master/examples/rot
+under a GPLv2+ license.

led_counterclockwise/pinmap_ct256.pcf

@@ -0,0 +1,10 @@
+# example.pcf
+set_io --warn-no-port led1 B5
+set_io --warn-no-port led2 B4
+set_io --warn-no-port led3 A2
+set_io --warn-no-port led4 A1
+set_io --warn-no-port led5 C5
+#set_io --warn-no-port led6 C4
+#set_io --warn-no-port led7 B3
+#set_io --warn-no-port led8 C3
+set_io --warn-no-port hwclk J3

led_counterclockwise/pinmap_tq144.pcf

@@ -0,0 +1,6 @@
+set_io D1 99
+set_io D2 98
+set_io D3 97
+set_io D4 96
+set_io D5 95
+set_io clk 21

led_counterclockwise/top.v

@@ -0,0 +1,32 @@
+module top(input clk, output D1, output D2, output D3, output D4, output D5);
+
+   reg ready = 0;
+   reg [23:0]     divider;
+   reg [3:0]      rot;
+
+   always @(posedge clk) begin
+      if (ready) 
+    begin
+       if (divider == 12000000) 
+         begin
+        divider <= 0;
+        // rot <= {rot[2:0], rot[3]}; // clockwise
+        rot <= {rot[0],rot[3:1]};     // counter clockwise
+         end
+       else 
+         divider <= divider + 1;
+    end 
+      else 
+    begin
+       ready <= 1;
+       rot <= 4'b0001;
+       divider <= 0;
+    end 
+   end 
+
+   assign D1 = rot[0];
+   assign D2 = rot[1];
+   assign D3 = rot[2];
+   assign D4 = rot[3];
+   assign D5 = 1;
+endmodule