replace cv32e40p with cv32e41p in files (#5)

* change module and file name to match cv32e41p * update capital letters in docs * update makefile and waves Signed-off-by: Pasquale Davide Schiavone <[email protected]>
openhwgroup · Jun 23, 2021 · 82fd61f · 82fd61f
1 parent 3c95739
commit 82fd61f
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diff --git a/Bender.yml b/Bender.yml
@@ -24,37 +24,37 @@ sources:
   include_dirs:
     - rtl/include
   files:
-    - rtl/include/cv32e40p_apu_core_pkg.sv
-    - rtl/include/cv32e40p_pkg.sv
-    - rtl/cv32e40p_alu.sv
-    - rtl/cv32e40p_alu_div.sv
-    - rtl/cv32e40p_aligner.sv
-    - rtl/cv32e40p_compressed_decoder.sv
-    - rtl/cv32e40p_controller.sv
-    - rtl/cv32e40p_cs_registers.sv
-    - rtl/cv32e40p_decoder.sv
-    - rtl/cv32e40p_int_controller.sv
-    - rtl/cv32e40p_ex_stage.sv
-    - rtl/cv32e40p_hwloop_controller.sv
-    - rtl/cv32e40p_hwloop_regs.sv
-    - rtl/cv32e40p_id_stage.sv
-    - rtl/cv32e40p_if_stage.sv
-    - rtl/cv32e40p_load_store_unit.sv
-    - rtl/cv32e40p_mult.sv
-    - rtl/cv32e40p_prefetch_buffer.sv
-    - rtl/cv32e40p_obi_interface.sv
-    - rtl/cv32e40p_core.sv
-    - rtl/cv32e40p_apu_disp.sv
-    - rtl/cv32e40p_fetch_fifo.sv
-    - rtl/cv32e40p_popcnt.sv
-    - rtl/cv32e40p_ff_one.sv
-    - rtl/cv32e40p_sleep_unit.sv
+    - rtl/include/cv32e41p_apu_core_pkg.sv
+    - rtl/include/cv32e41p_pkg.sv
+    - rtl/cv32e41p_alu.sv
+    - rtl/cv32e41p_alu_div.sv
+    - rtl/cv32e41p_aligner.sv
+    - rtl/cv32e41p_compressed_decoder.sv
+    - rtl/cv32e41p_controller.sv
+    - rtl/cv32e41p_cs_registers.sv
+    - rtl/cv32e41p_decoder.sv
+    - rtl/cv32e41p_int_controller.sv
+    - rtl/cv32e41p_ex_stage.sv
+    - rtl/cv32e41p_hwloop_controller.sv
+    - rtl/cv32e41p_hwloop_regs.sv
+    - rtl/cv32e41p_id_stage.sv
+    - rtl/cv32e41p_if_stage.sv
+    - rtl/cv32e41p_load_store_unit.sv
+    - rtl/cv32e41p_mult.sv
+    - rtl/cv32e41p_prefetch_buffer.sv
+    - rtl/cv32e41p_obi_interface.sv
+    - rtl/cv32e41p_core.sv
+    - rtl/cv32e41p_apu_disp.sv
+    - rtl/cv32e41p_fetch_fifo.sv
+    - rtl/cv32e41p_popcnt.sv
+    - rtl/cv32e41p_ff_one.sv
+    - rtl/cv32e41p_sleep_unit.sv
     - target: asic
       files:
-        - rtl/cv32e40p_register_file_latch.sv
+        - rtl/cv32e41p_register_file_latch.sv
     - target: not(asic)
       files:
-        - rtl/cv32e40p_register_file_ff.sv
+        - rtl/cv32e41p_register_file_ff.sv
     - target: rtl
       files:
-        - bhv/cv32e40p_sim_clock_gate.sv
+        - bhv/cv32e41p_sim_clock_gate.sv
diff --git a/bhv/cv32e40p_apu_tracer.sv → bhv/cv32e41p_apu_tracer.sv b/bhv/cv32e40p_apu_tracer.sv → bhv/cv32e41p_apu_tracer.sv
@@ -21,7 +21,7 @@
 ////////////////////////////////////////////////////////////////////////////////
 // Engineer:       Arjan Bink - [email protected]                         //
 //                                                                            //
-// Design Name:    cv32e40p_apu_tracer.sv (APU trace)                         //
+// Design Name:    cv32e41p_apu_tracer.sv (APU trace)                         //
 // Project Name:   CV32E40P                                                   //
 // Language:       SystemVerilog                                              //
 //                                                                            //
@@ -30,14 +30,14 @@
 //                 - APU register file write address                          //
 //                 - APU register file write data                             //
 //                                                                            //
-// Note:           This code was here from cv32e40p_core.sv in order to       //
+// Note:           This code was here from cv32e41p_core.sv in order to       //
 //                 remove the use of global defines in the RTL code.          //
 //                                                                            //
 ////////////////////////////////////////////////////////////////////////////////
 
 `ifdef CV32E40P_APU_TRACE
 
-module cv32e40p_apu_tracer (
+module cv32e41p_apu_tracer (
     input logic        clk_i,
     input logic        rst_n,
     input logic [31:0] hart_id_i,
@@ -74,6 +74,6 @@ module cv32e40p_apu_tracer (
     $fclose(apu_trace);
   end
 
-endmodule  // cv32e40p_apu_tracer
+endmodule  // cv32e41p_apu_tracer
 
 `endif  // CV32E40P_APU_TRACE
diff --git a/bhv/cv32e40p_core_log.sv → bhv/cv32e41p_core_log.sv b/bhv/cv32e40p_core_log.sv → bhv/cv32e41p_core_log.sv
@@ -21,7 +21,7 @@
 ////////////////////////////////////////////////////////////////////////////////
 // Engineer:       Arjan Bink - [email protected]                         //
 //                                                                            //
-// Design Name:    cv32e40p_core_log.sv (cv32e40p_core simulation log)        //
+// Design Name:    cv32e41p_core_log.sv (cv32e41p_core simulation log)        //
 // Project Name:   CV32E40P                                                   //
 // Language:       SystemVerilog                                              //
 //                                                                            //
@@ -30,13 +30,13 @@
 //                 - top level parameter settings                             //
 //                 - illegal instructions                                     //
 //                                                                            //
-// Note:           This code was here from cv32e40p_core.sv and               //
-//                 cv32e40p_controller.sv in order to remove the use of       //
+// Note:           This code was here from cv32e41p_core.sv and               //
+//                 cv32e41p_controller.sv in order to remove the use of       //
 //                 global defines in the RTL code.                            //
 //                                                                            //
 ////////////////////////////////////////////////////////////////////////////////
 
-module cv32e40p_core_log #(
+module cv32e41p_core_log #(
     parameter PULP_XPULP          =  1,                   // PULP ISA Extension (incl. custom CSRs and hardware loop, excl. p.elw) !!! HARDWARE LOOP IS NOT OPERATIONAL YET !!!
     parameter PULP_CLUSTER = 0,  // PULP Cluster interface (incl. p.elw)
     parameter FPU = 0,  // Floating Point Unit (interfaced via APU interface)
@@ -53,7 +53,7 @@ module cv32e40p_core_log #(
   // Log top level parameter values
   initial begin
     $display(
-        "[cv32e40p_core]: PULP_XPULP = %d, PULP_CLUSTER = %d, FPU %d, PULP_ZFINX %d, NUM_MHPMCOUNTERS %d",
+        "[cv32e41p_core]: PULP_XPULP = %d, PULP_CLUSTER = %d, FPU %d, PULP_ZFINX %d, NUM_MHPMCOUNTERS %d",
         PULP_XPULP, PULP_CLUSTER, FPU, PULP_ZFINX, NUM_MHPMCOUNTERS);
   end
 
@@ -65,4 +65,4 @@ module cv32e40p_core_log #(
     end
   end
 
-endmodule  // cv32e40p_core_log
+endmodule  // cv32e41p_core_log
diff --git a/bhv/cv32e40p_instr_trace.svh → bhv/cv32e41p_instr_trace.svh b/bhv/cv32e40p_instr_trace.svh → bhv/cv32e41p_instr_trace.svh
@@ -21,7 +21,7 @@
 ////////////////////////////////////////////////////////////////////////////////
 // Engineer:       Steve Richmond - [email protected]                 //
 //                                                                            //
-// Design Name:    cv32e40p_tracer data structures                            //
+// Design Name:    cv32e41p_tracer data structures                            //
 // Project Name:   CV32E40P                                                   //
 // Language:       SystemVerilog                                              //
 //                                                                            //

diff --git a/bhv/cv32e40p_sim_clock_gate.sv → bhv/cv32e41p_sim_clock_gate.sv b/bhv/cv32e40p_sim_clock_gate.sv → bhv/cv32e41p_sim_clock_gate.sv
@@ -8,11 +8,11 @@
 // CONDITIONS OF ANY KIND, either express or implied. See the License for the
 // specific language governing permissions and limitations under the License.
 
-// !!! cv32e40p_sim_clock_gate file is meant for simulation only !!!
+// !!! cv32e41p_sim_clock_gate file is meant for simulation only !!!
 // !!! It must not be used for ASIC synthesis                    !!!
 // !!! It must not be used for FPGA synthesis                    !!!
 
-module cv32e40p_clock_gate (
+module cv32e41p_clock_gate (
     input  logic clk_i,
     input  logic en_i,
     input  logic scan_cg_en_i,
@@ -27,4 +27,4 @@ module cv32e40p_clock_gate (
 
   assign clk_o = clk_i & clk_en;
 
-endmodule  // cv32e40p_clock_gate
+endmodule  // cv32e41p_clock_gate
diff --git a/bhv/cv32e40p_tracer.sv → bhv/cv32e41p_tracer.sv b/bhv/cv32e40p_tracer.sv → bhv/cv32e41p_tracer.sv
@@ -26,8 +26,8 @@
 
 `include "uvm_macros.svh"
 
-module cv32e40p_tracer
-  import cv32e40p_pkg::*;
+module cv32e41p_tracer
+  import cv32e41p_pkg::*;
   import uvm_pkg::*;
 (
   // Clock and Reset
@@ -96,7 +96,7 @@ module cv32e40p_tracer
   input  logic [ 4:0] imm_clip_type
 );
 
-  import cv32e40p_tracer_pkg::*;
+  import cv32e41p_tracer_pkg::*;
 
   // Make clock a bit to avoid x->0 transitions in tracer logic
   bit clk_i_d;
@@ -115,7 +115,7 @@ module cv32e40p_tracer
   logic [31:0] pc_wb_delay_stage;
   logic [31:0] pc_retire_head_q;
 
-`include "cv32e40p_instr_trace.svh"
+`include "cv32e41p_instr_trace.svh"
 
   string info_tag = "TRACER";
 
@@ -469,7 +469,7 @@ module cv32e40p_tracer
     end
   end
 
-endmodule : cv32e40p_tracer
+endmodule : cv32e41p_tracer
 
 
 `endif // CV32E40P_TRACE_EXECUTION
diff --git a/bhv/cv32e40p_wrapper.sv → bhv/cv32e41p_wrapper.sv b/bhv/cv32e40p_wrapper.sv → bhv/cv32e41p_wrapper.sv
@@ -8,25 +8,25 @@
 // CONDITIONS OF ANY KIND, either express or implied. See the License for the
 // specific language governing permissions and limitations under the License.
 
-// Wrapper for a cv32e40p, containing cv32e40p, and tracer
+// Wrapper for a cv32e41p, containing cv32e41p, and tracer
 // Contributor: Davide Schiavone <[email protected]>
 
 `ifdef CV32E40P_ASSERT_ON
-`include "cv32e40p_prefetch_controller_sva.sv"
+`include "cv32e41p_prefetch_controller_sva.sv"
 `endif
 
-`include "cv32e40p_core_log.sv"
+`include "cv32e41p_core_log.sv"
 
 `ifdef CV32E40P_APU_TRACE
-`include "cv32e40p_apu_tracer.sv"
+`include "cv32e41p_apu_tracer.sv"
 `endif
 
 `ifdef CV32E40P_TRACE_EXECUTION
-`include "cv32e40p_tracer.sv"
+`include "cv32e41p_tracer.sv"
 `endif
 
-module cv32e40p_wrapper
-  import cv32e40p_apu_core_pkg::*;
+module cv32e41p_wrapper
+  import cv32e41p_apu_core_pkg::*;
 #(
     parameter PULP_XPULP          =  0,                   // PULP ISA Extension (incl. custom CSRs and hardware loop, excl. p.elw)
     parameter PULP_CLUSTER = 0,  // PULP Cluster interface (incl. p.elw)
@@ -97,9 +97,9 @@ module cv32e40p_wrapper
 `ifdef CV32E40P_ASSERT_ON
 
   // RTL Assertions
-  bind cv32e40p_prefetch_controller:
+  bind cv32e41p_prefetch_controller:
       core_i.if_stage_i.prefetch_buffer_i.prefetch_controller_i
-      cv32e40p_prefetch_controller_sva
+      cv32e41p_prefetch_controller_sva
       #(
       .DEPTH          (DEPTH),
       .PULP_XPULP     (PULP_XPULP),
@@ -109,7 +109,7 @@ module cv32e40p_wrapper
 
 `endif  // CV32E40P_ASSERT_ON
 
-  cv32e40p_core_log #(
+  cv32e41p_core_log #(
       .PULP_XPULP      (PULP_XPULP),
       .PULP_CLUSTER    (PULP_CLUSTER),
       .FPU             (FPU),
@@ -124,7 +124,7 @@ module cv32e40p_wrapper
   );
 
 `ifdef CV32E40P_APU_TRACE
-  cv32e40p_apu_tracer apu_tracer_i (
+  cv32e41p_apu_tracer apu_tracer_i (
       .clk_i       (core_i.rst_ni),
       .rst_n       (core_i.clk_i),
       .hart_id_i   (core_i.hart_id_i),
@@ -135,7 +135,7 @@ module cv32e40p_wrapper
 `endif
 
 `ifdef CV32E40P_TRACE_EXECUTION
-  cv32e40p_tracer tracer_i (
+  cv32e41p_tracer tracer_i (
       .clk_i(core_i.clk_i),  // always-running clock for tracing
       .rst_n(core_i.rst_ni),
 
@@ -199,7 +199,7 @@ module cv32e40p_wrapper
 `endif
 
   // instantiate the core
-  cv32e40p_core #(
+  cv32e41p_core #(
       .PULP_XPULP      (PULP_XPULP),
       .PULP_CLUSTER    (PULP_CLUSTER),
       .FPU             (FPU),

diff --git a/bhv/include/cv32e40p_tracer_pkg.sv → bhv/include/cv32e41p_tracer_pkg.sv b/bhv/include/cv32e40p_tracer_pkg.sv → bhv/include/cv32e41p_tracer_pkg.sv
@@ -9,8 +9,8 @@
 // specific language governing permissions and limitations under the License.
 
 
-package cv32e40p_tracer_pkg;
-  import cv32e40p_pkg::*;
+package cv32e41p_tracer_pkg;
+  import cv32e41p_pkg::*;
 
   // settings
   parameter bit SymbolicRegs = 0;  // show abi names for registers

diff --git a/constraints/cv32e40p_core.sdc → constraints/cv32e41p_core.sdc b/constraints/cv32e40p_core.sdc → constraints/cv32e41p_core.sdc
diff --git a/cv32e40p_manifest.flist b/cv32e40p_manifest.flist