Convert documentation to CV32E41P (#19)

* Convert documentation to CV32E41P * Update links and Verible version * Add comments about the RTL status Co-authored-by: Tariq Kurd <[email protected]>
openhwgroup · Feb 14, 2022 · d432b96 · d432b96
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diff --git a/README.md b/README.md
@@ -5,9 +5,7 @@
 CV32E41P is a small and efficient, 32-bit, in-order RISC-V core with a 4-stage pipeline that implements
 the RV32IM\[F,Zfinx\]C\[Zce\] instruction set architecture, and the Xpulp custom extensions for achieving
 higher code density, performance, and energy efficiency \[[1](https://doi.org/10.1109/TVLSI.2017.2654506)\], \[[2](https://doi.org/10.1109/PATMOS.2017.8106976)\].
-It started its life as a fork of the CV32E40P core to implement the official RISC-V [Zfinx](https://github.com/riscv/riscv-zfinx/blob/main/zfinx-spec-20210511-0.41.pdf) and [Zce](https://github.com/riscv/riscv-code-size-reduction/blob/master/ISA%20proposals/Huawei/Zce_spec.adoc) ISA extensions.
-
-A first implementation of the Zce ISA extensions has been explored in \[[3](https://www.research-collection.ethz.ch/bitstream/handle/20.500.11850/461404/1/CARRV2020_paper_12_Perotti.pdf)\] to investigate code reduction benefits.
+It started its life as a fork of the CV32E40P core to implement the official RISC-V [Zfinx](https://github.com/riscv/riscv-zfinx/blob/main/zfinx-spec-20210511-0.41.pdf) and [Zce](https://github.com/riscv/riscv-code-size-reduction/releases/tag/V0.50.1-TOOLCHAIN-DEV) ISA extensions.
 
 ## Documentation
 
@@ -46,27 +44,13 @@ When contributing SystemVerilog source code, please try to be consistent and adh
 coding style guide](https://github.com/lowRISC/style-guides/blob/master/VerilogCodingStyle.md).
 
 To get started, please check out the ["Good First Issue"
- list](https://github.com/openhwgroup/cv32e40p/issues?q=is%3Aissue+is%3Aopen+-label%3Astatus%3Aresolved+label%3A%22good+first+issue%22).
+ list](https://github.com/openhwgroup/cv32e41p/issues?q=is%3Aissue+is%3Aopen+-label%3Astatus%3Aresolved+label%3A%22good+first+issue%22).
 
-The RTL code has been formatted with ["Verible"](https://github.com/google/verible) v0.0-1149-g7eae750.
+The RTL code has been formatted with ["Verible"](https://github.com/google/verible) v0.0-1824-ga3b5bedf.
 
 ## Issues and Troubleshooting
 
 If you find any problems or issues with CV32E41P or the documentation, please check out the [issue
- tracker](https://github.com/openhwgroup/cv32e40p/issues) and create a new issue if your problem is
+ tracker](https://github.com/openhwgroup/cv32e41p/issues) and create a new issue if your problem is
 not yet tracked.
 
-## References
-
-1. [Gautschi, Michael, et al. "Near-Threshold RISC-V Core With DSP Extensions for Scalable IoT Endpoint Devices."
- in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 10, pp. 2700-2713, Oct. 2017](https://doi.org/10.1109/TVLSI.2017.2654506)
-
-2. [Schiavone, Pasquale Davide, et al. "Slow and steady wins the race? A comparison of
- ultra-low-power RISC-V cores for Internet-of-Things applications."
- _27th International Symposium on Power and Timing Modeling, Optimization and Simulation
- (PATMOS 2017)_](https://doi.org/10.1109/PATMOS.2017.8106976)
-
-3. [Perotti, Matteo, et al. "HW/SW approaches for RISC-V code size reduction."
- Workshop on Computer Architecture Research with RISC-V (CARRV 2020). 2020.](https://www.research-collection.ethz.ch/bitstream/handle/20.500.11850/461404/1/CARRV2020_paper_12_Perotti.pdf)
-
-
diff --git a/docs/source/apu.rst b/docs/source/apu.rst
@@ -63,7 +63,7 @@ The CV32E41P apu interface can cause up to two outstanding transactions.
 Connection with the FPU
 -----------------------
 
-The CV32E41P sends FP operands over the ``apu_operands_o`` bus; the decoded RV32F operation as ADD, SUB, MUL, etc through the ``apu_op_o`` bus; the cast, destination and source formats as well as rounding mode through the ``apu_flags_o`` bus. The respose is the FPU result and relative output flags as Overflow, Underflow, etc.
+The CV32E41P sends FP operands over the ``apu_operands_o`` bus; the decoded RV32F operation as ADD, SUB, MUL, etc through the ``apu_op_o`` bus; the cast, destination and source formats as well as rounding mode through the ``apu_flags_o`` bus. The response is the FPU result and relative output flags as Overflow, Underflow, etc.
 
 
 APU Tracer

diff --git a/docs/source/control_status_registers.rst b/docs/source/control_status_registers.rst
@@ -442,71 +442,30 @@ Detailed:
 +=============+============+========================================================================+
 | 31:30       | RO   (0x1) |  **MXL** (Machine XLEN).                                               |
 +-------------+------------+------------------------------------------------------------------------+
-| 29:26       | RO   (0x0) | (Reserved).                                                            |
-+-------------+------------+------------------------------------------------------------------------+
-| 25          | RO   (0x0) | **Z** (Reserved). Read-only; writes are ignored.                       |
-+-------------+------------+------------------------------------------------------------------------+
-| 24          | RO   (0x0) | **Y** (Reserved).                                                      |
-+-------------+------------+------------------------------------------------------------------------+
 | 23          | RO         | **X** (Non-standard extensions present).                               |
 +-------------+------------+------------------------------------------------------------------------+
-| 22          | RO   (0x0) | **W** (Reserved).                                                      |
-+-------------+------------+------------------------------------------------------------------------+
-| 21          | RO   (0x0) | **V** (Tentatively reserved for Vector extension).                     |
-+-------------+------------+------------------------------------------------------------------------+
-| 20          | RO   (0x0) | **U** (User mode implemented).                                         |
-+-------------+------------+------------------------------------------------------------------------+
-| 19          | RO   (0x0) | **T** (Tentatively reserved for Transactional Memory extension).       |
-+-------------+------------+------------------------------------------------------------------------+
-| 18          | RO   (0x0) | **S** (Supervisor mode implemented).                                   |
-+-------------+------------+------------------------------------------------------------------------+
-| 17          | RO   (0x0) | **R** (Reserved).                                                      |
-+-------------+------------+------------------------------------------------------------------------+
-| 16          | RO   (0x0) | **Q** (Quad-precision floating-point extension).                       |
-+-------------+------------+------------------------------------------------------------------------+
-| 15          | RO   (0x0) | **P** (Tentatively reserved for Packed-SIMD extension).                |
-+-------------+------------+------------------------------------------------------------------------+
-| 14          | RO   (0x0) | **O** (Reserved).                                                      |
-+-------------+------------+------------------------------------------------------------------------+
-| 13          | RO   (0x0) | **N** (User-level interrupts supported).                               |
-+-------------+------------+------------------------------------------------------------------------+
 | 12          | RO   (0x1) | **M** (Integer Multiply/Divide extension).                             |
 +-------------+------------+------------------------------------------------------------------------+
-| 11          | RO   (0x0) | **L** (Tentatively reserved for Decimal Floating-Point extension).     |
-+-------------+------------+------------------------------------------------------------------------+
-| 10          | RO   (0x0) | **K** (Reserved).                                                      |
-+-------------+------------+------------------------------------------------------------------------+
-| 9           | RO   (0x0) | **J** (Tentatively reserved for Dynamically Translated Languages       |
-|             |            | extension).                                                            |
-+-------------+------------+------------------------------------------------------------------------+
 | 8           | RO   (0x1) | **I** (RV32I/64I/128I base ISA).                                       |
 +-------------+------------+------------------------------------------------------------------------+
-| 7           | RO   (0x0) | **H** (Hypervisor extension).                                          |
-+-------------+------------+------------------------------------------------------------------------+
-| 6           | RO   (0x0) | **G** (Additional standard extensions present).                        |
-+-------------+------------+------------------------------------------------------------------------+
 | 5           | RO         | **F** (Single-precision floating-point extension).                     |
 +-------------+------------+------------------------------------------------------------------------+
-| 4           | RO   (0x0) | **E** (RV32E base ISA).                                                |
-+-------------+------------+------------------------------------------------------------------------+
-| 3           | RO   (0x0) | **D** (Double-precision floating-point extension).                     |
-+-------------+------------+------------------------------------------------------------------------+
 | 2           | RO   (0x1) | **C** (Compressed extension).                                          |
 +-------------+------------+------------------------------------------------------------------------+
-| 1           | RO   (0x0) | **B** (Tentatively reserved for Bit-Manipulation extension).           |
-+-------------+------------+------------------------------------------------------------------------+
-| 0           | RO   (0x0) | **A** (Atomic extension).                                              |
+| others      | RO   (0x0) | All other fields read as zero                                          |
 +-------------+------------+------------------------------------------------------------------------+
 
 All bitfields in the ``misa`` CSR read as 0 except for the following:
 
 * **C** = 1
-* **F** = 1 if ``FPU`` = 1
+* **F** = 1 if ``FPU`` = 1 and ``ZFINX`` = 0
 * **I** = 1
 * **M** = 1
 * **X** = 1 if ``PULP_XPULP`` = 1 or ``PULP_CLUSTER`` = 1
 * **MXL** = 1 (i.e. XLEN = 32)
 
+The bit positions are shown in the table above.
+
 Machine Interrupt Enable Register (``mie``)
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 

diff --git a/docs/source/core_versions.rst b/docs/source/core_versions.rst
@@ -23,9 +23,7 @@ The tuple identify which sets of parameters have been verified
 by OpenHW Group, and once RTL Freeze is achieved, no further
 non-logically equivalent changes are allowed on that set of parameters.
 
-The RTL Freeze version of the core is indentified by a GitHub
-tag with the format cv32e41p_vMAJOR.MINOR.PATCH (e.g. cv32e41p_v1.0.0).
-In addition, the release date is reported in the documentation.
+The core RTL is not yet frozen, but it's kept sequentially equivalent to CV32E40P for the RV32IMC subset except for don't care states.
 
 What happens after RTL Freeze?
 ------------------------------
@@ -40,13 +38,13 @@ value and the bug and the fix must be documented.
 These changes are visible by software as the ``mimpid`` has a different value.
 Every bug or set of bugs found must be followed by another RTL Freeze release and a new GitHub tag.
 
-RTL changes on non-verified yet parameters
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+RTL changes on unverified parameters
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
 If changes affecting the core on a non-frozen parameter set are required,
 as for example, to fix bugs found in the communication to the FPU (e.g., affecting the core only if ``FPU=1``),
 or to change the ISA Extensions decoding of PULP instructions (e.g., affecting the core only if ``PULP_XPULP=1``),
-then such changes must remain logically equivalent for the already frozen set of parameters (except for the required mimpid update), and they must be applied on a different ``mimpid`` value. They can be non-logically equivalent to a non-frozen set of parameters.
+then such changes must remain logically equivalent for the already frozen set of parameters (except for the required ``mimpid`` update), and they must be applied on a different ``mimpid`` value. They can be non-logically equivalent to a non-frozen set of parameters.
 These changes are visible by software as the ``mimpid`` has a different value.
 Once the new set of parameters is verified and achieved the sign-off for RTL freeze,
 a new GitHub tag and version of the core is released.
@@ -60,21 +58,11 @@ If PPA optimizations are logically-equivalent instead, they can be applied witho
 changing the ``mimpid`` value (as such changes are not visible in software).
 However, a new GitHub tag should be release and changes documented.
 
-:numref:`rtl_freeze_rules` shows the aforementioned rules.
-
-.. figure:: ../images/rtl_freeze_rules.png
-   :name: rtl_freeze_rules
-   :align: center
-   :alt:
-
-   Versions control of CV32E41P
-
-
 Released core versions
 ----------------------
 
 The verified parameter sets of the core, their implementation version, GitHub tags,
-and dates are reported here.
+and dates will be reported here.
 
 ``mimpid=0``
 ------------
@@ -84,27 +72,21 @@ The ``mimpid=0`` refers to the CV32E41P core verified with the following paramet
 +---------------------------+-------+
 | Name                      | Value |
 +===========================+=======+
-| ``FPU``                   |   0   |
-+---------------------------+-------+
 | ``NUM_MHPMCOUNTERS``      |   1   |
 +---------------------------+-------+
 | ``PULP_CLUSTER``          |   0   |
 +---------------------------+-------+
 | ``PULP_XPULP``            |   0   |
 +---------------------------+-------+
-| ``PULP_ZFINX``            |   0   |
+| ``FPU``                   |   0   |
++---------------------------+-------+
+| ``ZFINX``                 |   0   |
++---------------------------+-------+
+| ``Zcea``                  |   0   |
++---------------------------+-------+
+| ``Zceb``                  |   0   |
++---------------------------+-------+
+| ``Zcec``                  |   0   |
++---------------------------+-------+
+| ``Zcee``                  |   0   |
 +---------------------------+-------+
-
-Following, all the GitHub tags related to ``mimpid=0``.
-
-+--------------------+-------------------+------------+--------------------+---------+
-| Git Tag            | Tagged By         | Date       | Reason for Release | Comment |
-+====================+===================+============+====================+=========+
-| cv32e41p_v1.0.0    | Arjan Bink        | 2020-12-10 | RTL Freeze         |         |
-+--------------------+-------------------+------------+--------------------+---------+
-
-The list of open (waived) issues at the time of applying the cv32e41p_v1.0.0 tag can be found at:
-
-* https://github.com/openhwgroup/core-v-docs/blob/master/program/milestones/CV32E41P/RTL_Freeze_v1.0.0/Design_openissues.md
-* https://github.com/openhwgroup/core-v-docs/blob/master/program/milestones/CV32E41P/RTL_Freeze_v1.0.0/Verification_openissues.md
-* https://github.com/openhwgroup/core-v-docs/blob/master/program/milestones/CV32E41P/RTL_Freeze_v1.0.0/Documentation_openissues.md
diff --git a/docs/source/fpu.rst b/docs/source/fpu.rst
@@ -31,7 +31,7 @@ In the core repository, a wrapper showing how the FPU is connected
 to the core is available at ``example_tb/core/cv32e41p_fp_wrapper.sv``.
 By default a dedicated register file consisting of 32
 floating-point registers, ``f0``-``f31``, is instantiated. This default behavior
-can be overruled by setting the parameter **PULP_ZFINX** of the toplevel
+can be overruled by setting the parameter **ZFINX** of the toplevel
 file ``cv32e41p_core.sv`` to 1, in which case the dedicated register file is
 not included and the general purpose register file is used instead to
 host the floating-point operands.

diff --git a/docs/source/integration.rst b/docs/source/integration.rst
@@ -33,7 +33,11 @@ Instantiation Template
       .NUM_MHPMCOUNTERS         ( 1 ),
       .PULP_CLUSTER             ( 0 ),
       .PULP_XPULP               ( 0 ),
-      .PULP_ZFINX               ( 0 )
+      .ZFINX                    ( 0 )
+      .Zcea                     ( 0 ) //FIXME these will change names
+      .Zceb                     ( 0 ) //when moving to v0.70 
+      .Zcec                     ( 0 )
+      .Zcee                     ( 0 )
   ) u_core (
       // Clock and reset
       .clk_i                    (),
@@ -95,7 +99,7 @@ Parameters
 ----------
 
 .. note::
-   The non-default (i.e. non-zero) settings of ``FPU``, ``PULP_CLUSTER``, ``PULP_XPULP`` and ``PULP_ZFINX`` have not
+   The non-default (i.e. non-zero) settings of ``FPU``, ``PULP_CLUSTER``, ``PULP_XPULP`` and ``ZFINX`` have not
    been verified yet. The default parameter value for ``PULP_XPULP`` will be changed to 1 once it has been verified.
    The default configuration reflected below is currently under verification and this verification effort will be
    completed first.
@@ -124,11 +128,19 @@ Parameters
 |                              |             |            | (see :ref:`corev_hardware_loop`).                                |
 |                              |             |            |                                                                  |
 +------------------------------+-------------+------------+------------------------------------------------------------------+
-| ``PULP_ZFINX``               | bit         | 0          | Enable Floating Point instructions to use the General Purpose    |
+| ``ZFINX``                    | bit         | 0          | Enable Floating Point instructions to use the General Purpose    |
 |                              |             |            | register file instead of requiring a dedicated Floating Point    |
 |                              |             |            | register file, see :ref:`fpu`. Only allowed to be set to 1       |
 |                              |             |            | if ``FPU`` = 1                                                   |
 +------------------------------+-------------+------------+------------------------------------------------------------------+
+| ``Zcea``                     | bit         | 0          | Enable all Zcea instruction from Zce v0.50.1                     |
++------------------------------+-------------+------------+------------------------------------------------------------------+
+| ``Zceb``                     | bit         | 0          | Enable all Zceb instruction from Zce v0.50.1                     |
++------------------------------+-------------+------------+------------------------------------------------------------------+
+| ``Zcec``                     | bit         | 0          | Enable all Zcec instruction from Zce v0.50.1                     |
++------------------------------+-------------+------------+------------------------------------------------------------------+
+| ``Zcee``                     | bit         | 0          | Enable all Zcee instruction from Zce v0.50.1                     |
++------------------------------+-------------+------------+------------------------------------------------------------------+
 
 Interfaces
 ----------