Change PULP_ZFINX to ZFINX (#21)

openhwgroup · Mar 7, 2022 · f22dca3 · f22dca3
1 parent 61c9913
commit f22dca3
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Showing 10 changed files with 45 additions and 41 deletions.
diff --git a/bhv/cv32e41p_core_log.sv b/bhv/cv32e41p_core_log.sv
@@ -40,7 +40,7 @@ module cv32e41p_core_log #(
     parameter PULP_XPULP          =  1,                   // PULP ISA Extension (incl. custom CSRs and hardware loop, excl. p.elw) !!! HARDWARE LOOP IS NOT OPERATIONAL YET !!!
     parameter PULP_CLUSTER = 0,  // PULP Cluster interface (incl. p.elw)
     parameter FPU = 0,  // Floating Point Unit (interfaced via APU interface)
-    parameter PULP_ZFINX = 0,  // Float-in-General Purpose registers
+    parameter ZFINX = 0,  // Float-in-General Purpose registers
     parameter NUM_MHPMCOUNTERS = 1
 ) (
     input logic        clk_i,
@@ -53,8 +53,8 @@ module cv32e41p_core_log #(
   // Log top level parameter values
   initial begin
     $display(
-        "[cv32e41p_core]: PULP_XPULP = %d, PULP_CLUSTER = %d, FPU %d, PULP_ZFINX %d, NUM_MHPMCOUNTERS %d",
-        PULP_XPULP, PULP_CLUSTER, FPU, PULP_ZFINX, NUM_MHPMCOUNTERS);
+        "[cv32e41p_core]: PULP_XPULP = %d, PULP_CLUSTER = %d, FPU %d, ZFINX %d, NUM_MHPMCOUNTERS %d",
+        PULP_XPULP, PULP_CLUSTER, FPU, ZFINX, NUM_MHPMCOUNTERS);
   end
 
   // Log illegal instructions

diff --git a/bhv/cv32e41p_wrapper.sv b/bhv/cv32e41p_wrapper.sv
@@ -28,10 +28,10 @@
 module cv32e41p_wrapper
   import cv32e41p_apu_core_pkg::*;
 #(
-    parameter PULP_XPULP          =  0,  // PULP ISA Extension (incl. custom CSRs and hardware loop, excl. p.elw)
+    parameter PULP_XPULP          =  0,   // PULP ISA Extension (incl. custom CSRs and hardware loop, excl. p.elw)
     parameter PULP_CLUSTER = 0,  // PULP Cluster interface (incl. p.elw)
     parameter FPU = 0,  // Floating Point Unit (interfaced via APU interface)
-    parameter PULP_ZFINX = 0,  // Float-in-General Purpose registers
+    parameter ZFINX = 0,  // Float-in-General Purpose registers
     parameter Zcea = 0,
     parameter Zceb = 0,
     parameter Zcec = 0,
@@ -117,7 +117,7 @@ module cv32e41p_wrapper
       .PULP_XPULP      (PULP_XPULP),
       .PULP_CLUSTER    (PULP_CLUSTER),
       .FPU             (FPU),
-      .PULP_ZFINX      (PULP_ZFINX),
+      .ZFINX           (ZFINX),
       .NUM_MHPMCOUNTERS(NUM_MHPMCOUNTERS)
   ) core_log_i (
       .clk_i             (core_i.id_stage_i.clk),
@@ -207,7 +207,7 @@ module cv32e41p_wrapper
       .PULP_XPULP      (PULP_XPULP),
       .PULP_CLUSTER    (PULP_CLUSTER),
       .FPU             (FPU),
-      .PULP_ZFINX      (PULP_ZFINX),
+      .ZFINX           (ZFINX),
       .Zcea            (Zcea),
       .Zceb            (Zceb),
       .Zcec            (Zcec),

diff --git a/example_tb/core/cv32e41p_tb_subsystem.sv b/example_tb/core/cv32e41p_tb_subsystem.sv
@@ -18,7 +18,7 @@ module cv32e41p_tb_subsystem #(
     parameter PULP_XPULP = 0,
     parameter PULP_CLUSTER = 0,
     parameter FPU = 0,
-    parameter PULP_ZFINX = 0,
+    parameter ZFINX = 0,
     parameter NUM_MHPMCOUNTERS = 1,
     parameter DM_HALTADDRESS = 32'h1A110800
 ) (
@@ -87,7 +87,7 @@ module cv32e41p_tb_subsystem #(
       .PULP_XPULP      (PULP_XPULP),
       .PULP_CLUSTER    (PULP_CLUSTER),
       .FPU             (FPU),
-      .PULP_ZFINX      (PULP_ZFINX),
+      .ZFINX      (ZFINX),
       .NUM_MHPMCOUNTERS(NUM_MHPMCOUNTERS)
   ) wrapper_i (
       .clk_i (clk_i),

diff --git a/example_tb/core/tb_top.sv b/example_tb/core/tb_top.sv
@@ -20,7 +20,7 @@ module tb_top #(
     parameter PULP_XPULP = 0,
     parameter PULP_CLUSTER = 0,
     parameter FPU = 0,
-    parameter PULP_ZFINX = 0,
+    parameter ZFINX = 0,
     parameter NUM_MHPMCOUNTERS = 1,
     parameter DM_HALTADDRESS = 32'h1A110800
 );
@@ -149,7 +149,7 @@ module tb_top #(
       .PULP_XPULP       (PULP_XPULP),
       .PULP_CLUSTER     (PULP_CLUSTER),
       .FPU              (FPU),
-      .PULP_ZFINX       (PULP_ZFINX),
+      .ZFINX       (ZFINX),
       .NUM_MHPMCOUNTERS (NUM_MHPMCOUNTERS),
       .DM_HALTADDRESS   (DM_HALTADDRESS)
   ) wrapper_i (

diff --git a/rtl/cv32e41p_core.sv b/rtl/cv32e41p_core.sv
@@ -38,7 +38,7 @@ module cv32e41p_core
     parameter Zceb = 0,  // 
     parameter Zcec = 0,  // 
     parameter Zcee = 0,  // 
-    parameter PULP_ZFINX = 0,  // Float-in-General Purpose registers
+    parameter ZFINX = 0,  // Float-in-General Purpose registers
     parameter NUM_MHPMCOUNTERS = 1
 ) (
     // Clock and Reset
@@ -525,7 +525,7 @@ module cv32e41p_core
       .A_EXTENSION     (A_EXTENSION),
       .APU             (APU),
       .FPU             (FPU),
-      .PULP_ZFINX      (PULP_ZFINX),
+      .ZFINX           (ZFINX),
       .APU_NARGS_CPU   (APU_NARGS_CPU),
       .APU_WOP_CPU     (APU_WOP_CPU),
       .APU_NDSFLAGS_CPU(APU_NDSFLAGS_CPU),
@@ -938,6 +938,7 @@ module cv32e41p_core
   cv32e41p_cs_registers #(
       .A_EXTENSION     (A_EXTENSION),
       .FPU             (FPU),
+      .ZFINX           (ZFINX),
       .APU             (APU),
       .PULP_SECURE     (PULP_SECURE),
       .USE_PMP         (USE_PMP),
@@ -1138,7 +1139,7 @@ module cv32e41p_core
   // Assertions
   //----------------------------------------------------------------------------
 
-  // PULP_XPULP, PULP_CLUSTER, FPU, PULP_ZFINX
+  // PULP_XPULP, PULP_CLUSTER, FPU, ZFINX
   always_ff @(posedge rst_ni) begin
     if (PULP_XPULP) begin
       $warning(
@@ -1150,8 +1151,8 @@ module cv32e41p_core
     if (FPU) begin
       $warning("FPU == 1 has not been verified yet");
     end
-    if (PULP_ZFINX) begin
-      $warning("PULP_ZFINX == 1 has not been verified yet");
+    if (ZFINX) begin
+      $warning("ZFINX == 1 has not been verified yet");
     end
   end
 

diff --git a/rtl/cv32e41p_cs_registers.sv b/rtl/cv32e41p_cs_registers.sv
@@ -35,6 +35,7 @@ module cv32e41p_cs_registers
     parameter APU              = 0,
     parameter A_EXTENSION      = 0,
     parameter FPU              = 0,
+    parameter ZFINX            = 0,
     parameter PULP_SECURE      = 0,
     parameter USE_PMP          = 0,
     parameter N_PMP_ENTRIES    = 16,
@@ -166,7 +167,7 @@ module cv32e41p_cs_registers
   | (1 << 2)  // C - Compressed extension
   | (0 << 3)  // D - Double precision floating-point extension
   | (0 << 4)  // E - RV32E base ISA
-  | (32'(FPU) << 5)  // F - Single precision floating-point extension
+  | (32'(FPU & !ZFINX) << 5)  // F - Single precision floating-point extension
   | (1 << 8)  // I - RV32I/64I/128I base ISA
   | (1 << 12)  // M - Integer Multiply/Divide extension
   | (0 << 13)  // N - User level interrupts supported

diff --git a/rtl/cv32e41p_id_stage.sv b/rtl/cv32e41p_id_stage.sv
@@ -44,7 +44,7 @@ module cv32e41p_id_stage
     parameter A_EXTENSION = 0,
     parameter APU = 0,
     parameter FPU = 0,
-    parameter PULP_ZFINX = 0,
+    parameter ZFINX = 0,
     parameter APU_NARGS_CPU = 3,
     parameter APU_WOP_CPU = 6,
     parameter APU_NDSFLAGS_CPU = 15,
@@ -563,7 +563,7 @@ module cv32e41p_id_stage
   //-- FPU Register file enable:
   //-- Taken from Cluster Config Reg if FPU reg file exists, or always disabled
   //-----------------------------------------------------------------------------
-  assign fregfile_ena = FPU && !PULP_ZFINX ? 1'b1 : 1'b0;
+  assign fregfile_ena = FPU && !ZFINX ? 1'b1 : 1'b0;
 
   //---------------------------------------------------------------------------
   // source register selection regfile_fp_x=1 <=> CV32E40P_REG_x is a FP-register
@@ -976,7 +976,7 @@ module cv32e41p_id_stage
       .ADDR_WIDTH(6),
       .DATA_WIDTH(32),
       .FPU       (FPU),
-      .PULP_ZFINX(PULP_ZFINX)
+      .ZFINX     (ZFINX)
   ) register_file_i (
       .clk  (clk),
       .rst_n(rst_n),
@@ -1025,6 +1025,7 @@ module cv32e41p_id_stage
       .PULP_CLUSTER    (PULP_CLUSTER),
       .A_EXTENSION     (A_EXTENSION),
       .FPU             (FPU),
+      .ZFINX           (ZFINX),
       .PULP_SECURE     (PULP_SECURE),
       .USE_PMP         (USE_PMP),
       .APU_WOP_CPU     (APU_WOP_CPU),

diff --git a/rtl/cv32e41p_merged_decoder.sv b/rtl/cv32e41p_merged_decoder.sv
@@ -35,6 +35,7 @@ module cv32e41p_merged_decoder import cv32e41p_pkg::*; import cv32e41p_apu_core_
   parameter PULP_CLUSTER      = 0,
   parameter A_EXTENSION       = 0,
   parameter FPU               = 0,
+  parameter ZFINX             = 0,
   parameter PULP_SECURE       = 0,
   parameter USE_PMP           = 0,
   parameter APU_WOP_CPU       = 6,
@@ -1650,7 +1651,7 @@ module cv32e41p_merged_decoder import cv32e41p_pkg::*; import cv32e41p_apu_core_
                   fp_op_group = NONCOMP;
                   check_fprm  = 1'b0; // instruction encoded in rm, do the check here
                   // fmv.x.fmt - FPR to GPR Move
-                  if (instr_rdata_i[14:12] == 3'b000 || (C_XF16ALT && instr_rdata_i[14:12] == 3'b100)) begin
+                  if (ZFINX == 1'b0 && (instr_rdata_i[14:12] == 3'b000 || (C_XF16ALT && instr_rdata_i[14:12] == 3'b100))) begin
                     alu_op_b_mux_sel_o  = OP_B_REGA_OR_FWD; // set rs2 = rs1 so we can map FMV to SGNJ in the unit
                     fpu_op              = cv32e41p_fpu_pkg::SGNJ; // mapped to SGNJ-passthrough since no recoding
                     fpu_op_mod          = 1'b1;    // sign-extend result
@@ -1685,7 +1686,7 @@ module cv32e41p_merged_decoder import cv32e41p_pkg::*; import cv32e41p_apu_core_
                   fp_op_group         = NONCOMP;
                   fp_rnd_mode_o       = 3'b011;  // passthrough without checking nan-box
                   check_fprm          = 1'b0; // instruction encoded in rm, do the check here
-                  if (instr_rdata_i[14:12] == 3'b000 || (C_XF16ALT && instr_rdata_i[14:12] == 3'b100)) begin
+                  if (ZFINX == 1'b0 && (instr_rdata_i[14:12] == 3'b000 || (C_XF16ALT && instr_rdata_i[14:12] == 3'b100))) begin
                     // FP16ALT uses special encoding here
                     if (instr_rdata_i[14]) begin
                       fpu_dst_fmt_o = cv32e41p_fpu_pkg::FP16ALT;
@@ -1930,7 +1931,7 @@ module cv32e41p_merged_decoder import cv32e41p_pkg::*; import cv32e41p_apu_core_
           end
 
           OPCODE_LOAD_FP: begin
-            if (FPU==1) begin
+            if (FPU==1 && ZFINX==1'b0) begin
               data_req            = 1'b1;
               regfile_mem_we      = 1'b1;
               reg_fp_d_o          = 1'b1;
@@ -2657,7 +2658,7 @@ module cv32e41p_merged_decoder import cv32e41p_pkg::*; import cv32e41p_apu_core_
               end
             // c.fld -> fld rd', imm(rs1')
               3'b001: begin
-                if (FPU == 1'b1 && C_RVD) begin
+                if (FPU == 1'b1 && C_RVD && ZFINX==1'b0) begin
                   data_req            = 1'b1;
                   regfile_mem_we      = 1'b1;
                   reg_fp_d_o          = 1'b1;
@@ -2713,7 +2714,7 @@ module cv32e41p_merged_decoder import cv32e41p_pkg::*; import cv32e41p_apu_core_
               end
             // c.flw -> flw rd', imm(rs1')
               3'b011: begin
-                if (FPU == 1'b1) begin
+                if (FPU == 1'b1 && ZFINX == 1'b0) begin
                   data_req            = 1'b1;
                   regfile_mem_we      = 1'b1;
                   reg_fp_d_o          = 1'b1;
@@ -2784,7 +2785,7 @@ module cv32e41p_merged_decoder import cv32e41p_pkg::*; import cv32e41p_apu_core_
               end
             // c.fsd -> fsd rs2', imm(rs1')
               3'b101: begin
-                if (FPU==1) begin
+                if (FPU==1 && C_RVD && ZFINX == 1'b0) begin
                   data_req            = 1'b1;
                   data_we_o           = 1'b1;
                   rega_used_o         = 1'b1;
@@ -2837,7 +2838,7 @@ module cv32e41p_merged_decoder import cv32e41p_pkg::*; import cv32e41p_apu_core_
               end
             // c.fsw -> fsw rs2', imm(rs1')
               3'b111: begin
-                if (FPU==1 && C_RVF) begin
+                if (FPU==1 && C_RVF && ZFINX == 1'b0) begin
                   data_req            = 1'b1;
                   data_we_o           = 1'b1;
                   rega_used_o         = 1'b1;
@@ -3111,7 +3112,7 @@ module cv32e41p_merged_decoder import cv32e41p_pkg::*; import cv32e41p_apu_core_
 
               3'b001: begin
                 // c.fldsp -> fld rd, imm(x2)
-                if (FPU==1 && C_RVD)
+                if (FPU==1 && C_RVD && ZFINX == 1'b0)
                 begin // instr_i[6:5] -> offset[4:3], instr_i[4:2] -> offset[8:6], instr_i[12] -> offset[5]
                   data_req            = 1'b1;
                   regfile_mem_we      = 1'b1;
@@ -3168,7 +3169,7 @@ module cv32e41p_merged_decoder import cv32e41p_pkg::*; import cv32e41p_apu_core_
 
               3'b011: begin
                 // c.flwsp -> flw rd, imm(x2)
-                if (FPU == 1 && C_RVF) begin
+                if (FPU == 1 && C_RVF && ZFINX == 1'b0) begin
                   data_req            = 1'b1;
                   regfile_mem_we      = 1'b1;
                   reg_fp_d_o          = 1'b1;
@@ -3270,7 +3271,7 @@ module cv32e41p_merged_decoder import cv32e41p_pkg::*; import cv32e41p_apu_core_
               3'b101: begin
                 // c.fsdsp -> fsd rs2, imm(x2)
                 // instr_i[12:10] -> offset[5:3], instr_i[9:7] -> offset[8:6]
-                if (FPU == 1 && C_RVD)  begin
+                if (FPU == 1 && C_RVD && ZFINX == 1'b0)  begin
                   data_req            = 1'b1;
                   data_we_o           = 1'b1;
                   rega_used_o         = 1'b1;
@@ -3309,7 +3310,7 @@ module cv32e41p_merged_decoder import cv32e41p_pkg::*; import cv32e41p_apu_core_
 
               3'b111: begin
                 // c.fswsp -> fsw rs2, imm(x2)
-                if (FPU == 1 && C_RVF) begin
+                if (FPU == 1 && C_RVF && ZFINX == 1'b0) begin
                   data_req            = 1'b1;
                   data_we_o           = 1'b1;
                   rega_used_o         = 1'b1;

diff --git a/rtl/cv32e41p_register_file_ff.sv b/rtl/cv32e41p_register_file_ff.sv
@@ -22,7 +22,7 @@
 // Description:    Register file with 31x 32 bit wide registers. Register 0   //
 //                 is fixed to 0. This register file is based on flip-flops.  //
 //                 Also supports the fp-register file now if FPU=1            //
-//                 If PULP_ZFINX is 1, floating point operations take values  //
+//                 If ZFINX is 1, floating point operations take values  //
 //                 from the X register file                                   //
 //                                                                            //
 ////////////////////////////////////////////////////////////////////////////////
@@ -31,7 +31,7 @@ module cv32e41p_register_file #(
     parameter ADDR_WIDTH = 5,
     parameter DATA_WIDTH = 32,
     parameter FPU        = 0,
-    parameter PULP_ZFINX = 0
+    parameter ZFINX      = 0
 ) (
     // Clock and Reset
     input logic clk,
@@ -66,7 +66,7 @@ module cv32e41p_register_file #(
   localparam NUM_WORDS = 2 ** (ADDR_WIDTH - 1);
   // number of floating point registers
   localparam NUM_FP_WORDS = 2 ** (ADDR_WIDTH - 1);
-  localparam NUM_TOT_WORDS = FPU ? (PULP_ZFINX ? NUM_WORDS : NUM_WORDS + NUM_FP_WORDS) : NUM_WORDS;
+  localparam NUM_TOT_WORDS = FPU ? (ZFINX ? NUM_WORDS : NUM_WORDS + NUM_FP_WORDS) : NUM_WORDS;
 
   // integer register file
   logic [    NUM_WORDS-1:0][DATA_WIDTH-1:0] mem;
@@ -87,7 +87,7 @@ module cv32e41p_register_file #(
   //-- READ : Read address decoder RAD
   //-----------------------------------------------------------------------------
   generate
-    if (FPU == 1 && PULP_ZFINX == 0) begin : gen_mem_fp_read
+    if (FPU == 1 && ZFINX == 0) begin : gen_mem_fp_read
       assign rdata_a_o = raddr_a_i[5] ? mem_fp[raddr_a_i[4:0]] : mem[raddr_a_i[4:0]];
       assign rdata_b_o = raddr_b_i[5] ? mem_fp[raddr_b_i[4:0]] : mem[raddr_b_i[4:0]];
       assign rdata_c_o = raddr_c_i[5] ? mem_fp[raddr_c_i[4:0]] : mem[raddr_c_i[4:0]];
@@ -145,7 +145,7 @@ module cv32e41p_register_file #(
 
     end
 
-    if (FPU == 1 && PULP_ZFINX == 0) begin : gen_mem_fp_write
+    if (FPU == 1 && ZFINX == 0) begin : gen_mem_fp_write
       // Floating point registers
       for (l = 0; l < NUM_FP_WORDS; l++) begin
         always_ff @(posedge clk, negedge rst_n) begin : fp_regs

diff --git a/rtl/cv32e41p_register_file_latch.sv b/rtl/cv32e41p_register_file_latch.sv
@@ -24,7 +24,7 @@
 //                 is fixed to 0. This register file is based on latches and  //
 //                 is thus smaller than the flip-flop based register file.    //
 //                 Also supports the fp-register file now if FPU=1            //
-//                 If PULP_ZFINX is 1, floating point operations take values  //
+//                 If ZFINX is 1, floating point operations take values  //
 //                 from the X register file                                   //
 //                                                                            //
 ////////////////////////////////////////////////////////////////////////////////
@@ -33,7 +33,7 @@ module cv32e41p_register_file #(
     parameter ADDR_WIDTH = 5,
     parameter DATA_WIDTH = 32,
     parameter FPU        = 0,
-    parameter PULP_ZFINX = 0
+    parameter ZFINX      = 0
 ) (
     // Clock and Reset
     input logic clk,
@@ -68,7 +68,7 @@ module cv32e41p_register_file #(
   localparam NUM_WORDS = 2 ** (ADDR_WIDTH - 1);
   // number of floating point registers
   localparam NUM_FP_WORDS = 2 ** (ADDR_WIDTH - 1);
-  localparam NUM_TOT_WORDS = FPU ? (PULP_ZFINX ? NUM_WORDS : NUM_WORDS + NUM_FP_WORDS) : NUM_WORDS;
+  localparam NUM_TOT_WORDS = FPU ? (ZFINX ? NUM_WORDS : NUM_WORDS + NUM_FP_WORDS) : NUM_WORDS;
 
   // integer register file
   logic [   DATA_WIDTH-1:0] mem            [NUM_WORDS];
@@ -98,7 +98,7 @@ module cv32e41p_register_file #(
   //-----------------------------------------------------------------------------
   //-- READ : Read address decoder RAD
   //-----------------------------------------------------------------------------
-  if (FPU == 1 && PULP_ZFINX == 0) begin
+  if (FPU == 1 && ZFINX == 0) begin
     assign rdata_a_o = raddr_a_i[5] ? mem_fp[raddr_a_i[4:0]] : mem[raddr_a_i[4:0]];
     assign rdata_b_o = raddr_b_i[5] ? mem_fp[raddr_b_i[4:0]] : mem[raddr_b_i[4:0]];
     assign rdata_c_o = raddr_c_i[5] ? mem_fp[raddr_c_i[4:0]] : mem[raddr_c_i[4:0]];
@@ -183,7 +183,7 @@ module cv32e41p_register_file #(
     end
   end
 
-  if (FPU == 1 && PULP_ZFINX == 0) begin
+  if (FPU == 1 && ZFINX == 0) begin
     // Floating point registers
     always_latch begin : latch_wdata_fp
       if (FPU == 1) begin