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RISC-V
The Open-Standard Instruction Set Architecture
- 3.9k followers
- Zurich, CH
- https://riscv.org
- @risc_v
- info@riscv.org
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- riscv-cheri Public
This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory protection and scalable compartmentalization.
riscv/riscv-cheri’s past year of commit activity - composable-custom-extensions Public
This task group will propose ISA extension(s) and non-ISA hardware and software interop interfaces to enable routine reuse and composition of a subcategory of custom extensions called composable extensions.
riscv/composable-custom-extensions’s past year of commit activity - sdtrigpend Public Forked from riscv/riscv-isa-manual
The intent of pending is to cleanly handle the case where action is 0, m is 0, u is 1, count is 1, and the U-mode instruction being executed causes a trap into M-mode.
riscv/sdtrigpend’s past year of commit activity - riscv-smmtt Public
This specification will define the RISC-V privilege ISA extensions required to support Supervisor Domain isolation for multi-tenant security use cases e.g. confidential-computing, trusted platform services, fault isolation and so on.
riscv/riscv-smmtt’s past year of commit activity - riscv-memory-tagging Public
Memory Tagging ISA extension that can be used by software to enforce memory tag checks on memory loads and stores
riscv/riscv-memory-tagging’s past year of commit activity - riscv-docs-base-container-image Public
A base container image populated with the dependencies to build the RISC-V Documentation.
riscv/riscv-docs-base-container-image’s past year of commit activity
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