I wanted to apply the concepts I had learnt in my Digital Systems classes and put together a basic turing machine. Projects such as Nand2Tetris and Ben Eater's 8-bit Breadboard computer also motivated me to make my own.
Due to no prior knowledge of a Hardware Description Language and being a beginner in the world of Digital Systems, I used Logisim Evolution to build the system.
I insisted on building every discrete component from scratch (instead of using built-in components) and with NAND gates only, to keep myself true to the Nand2Tetris course. Only the display was built from built-in components as it is considered an I/O device and not a part of the CPU.
This project is consists of two parts
- Hardware: The main digital logic design, made in Logisim Evolution, saved as
sutra_1.circ
- Software
- রচয়িতা / Rochoyita
rochoyita.py
: Assembler. Rochoyita Documentation - শিল্পী / Shilpi
shipli.py
: Image generator for the 64x32 1-bit demo display. Shilpi Documentation
- রচয়িতা / Rochoyita
- Single core, in-order, non pipelined
- RISC design: All instructions are 10-bits and executed within one cycle
- 10-bit data bus
- 20-bit address bus
- 1 General Purpose Shift Register and Accumulator(A)
- 3 General Purpose Registers (B, C, D)
- Flag Based ALU with hardware NAND/ADD/SUBTRACT
- IO
- 64x32 1-bit display
- 4 interrupt lines
- 10-bit output bus
- Stack support
- Hardware and Software Interrupts with Masking support
- Implement this on an FPGA
- Add pipelining
- Add out of order execution
- Make it superscalar
- Nand2Tetris
- EE102
- Lorenzo's Logisim-Evolution Fork for faster simulation clock speed
All components and designs are licensed under the GNU General Public License v3.0.