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Sutra-1 / সুত্র-1 / सूत्र-1

10-bit CPU and Assembler

Sutra-1 Main Screenshot

Introduction

I wanted to apply the concepts I had learnt in my Digital Systems classes and put together a basic turing machine. Projects such as Nand2Tetris and Ben Eater's 8-bit Breadboard computer also motivated me to make my own.

Due to no prior knowledge of a Hardware Description Language and being a beginner in the world of Digital Systems, I used Logisim Evolution to build the system.

I insisted on building every discrete component from scratch (instead of using built-in components) and with NAND gates only, to keep myself true to the Nand2Tetris course. Only the display was built from built-in components as it is considered an I/O device and not a part of the CPU.

Components

This project is consists of two parts

  • Hardware: The main digital logic design, made in Logisim Evolution, saved as sutra_1.circ
  • Software

Specifications

  • Single core, in-order, non pipelined
  • RISC design: All instructions are 10-bits and executed within one cycle
  • 10-bit data bus
  • 20-bit address bus
  • 1 General Purpose Shift Register and Accumulator(A)
  • 3 General Purpose Registers (B, C, D)
  • Flag Based ALU with hardware NAND/ADD/SUBTRACT
  • IO
    • 64x32 1-bit display
    • 4 interrupt lines
    • 10-bit output bus
  • Stack support
  • Hardware and Software Interrupts with Masking support

Documentation

Future plans

  • Implement this on an FPGA
  • Add pipelining
  • Add out of order execution
  • Make it superscalar

Special thanks

License

All components and designs are licensed under the GNU General Public License v3.0.