riscv v0.14.0

A new batch of RISC-V releases are now available at crates.io! Here we enumerate the most important changes, but please read the CHANGELOG.md files for further details

riscv v0.14.0

@rmsyn added new CSRs. Also, MSRV is now 1.67

riscv-peripheral v0.3.0

This crate experienced a full rework, so the code corresponding to RISC-V peripherals is more natural for PACS generated with svd2rust

riscv-rt v0.15.0

We added the device and memory features to allow PACs to simplify the linking process, similar to cortex-m-rt. If you enable these features, the link.x file will include the device.x and/or memory.x files. In this way, just including link.x in your binary is enough.

The __pre_init symbol has disappeared from riscv-rt by default. If you need it, you must activate the pre_init feature. Also, note that the riscv_rt::pre_init has been deprecated, as it is unsound to execute Rust code before RAM initialization. Instead, use assembly.

We removed weak symbols, as currently stable Rust does not support weak linkage and LTOs. Now, we use _default_* symbols. Once weak linkage is available in stable Rust, we plan to go back to weak symbols. Thanks, @rslawson !

riscv 0.13.0

riscv 0.12.0

• CSR writes are now all unsafe. Users can open an RFC to nominate certain CSRs to be safe (#209)
• All CSR fields are now generated using macros (thanks, @rmsyn !)
• PACs can now use the RISCV_MTVEC_ALIGN environment variable to set the vector table byte alignment ((thanks, @ia0 !)

riscv-rt 0.13.0

• Compatibility with RV32E and RV64E!
• Linker script is now more aligned with cortex-m-rt

riscv-target-parser 0.1.0

New utility crate to assist in build scripts of the RISC-V ecosystem. It is useful for determining which extensions are available, the base ISA of the target, etc.

riscv-peripheral 0.2.1 and riscv-semihosting 0.1.3

Update dependencies

`riscv` 0.12.0

New features

riscv 0.12.0

• Support for target-dependent external interrupt and exception numbers
• riscv-macros for helping during the definition of custom interrupt and exception sources
• Macros for automating the definition of new CSRs

riscv-pac 0.2.0

• Enumeration of common errors for RISC-V targets at the register level
• All PAC traits now work with usize numbers
• New ExceptionNumber trait for custom exception numbers

riscv-peripheral 0.2.0

• Adapt to new changes in the RISC-V ecosystem

riscv-rt 0.13.0

• Now exceptions rely on the _dispatch_exception function
• Now interrupts rely on the _dispatch_interrupt function
• While the crate provides a default implementation for the previously mentioned functions, you can skip these functions with the new no-exceptions and no-interrupts features. This way, you can adapt riscv-rt to target-specific sources.
• New pre_init_trap to detect early errors during the boot process.
• Vectored interrupts handling is now available under the v-trap feature!
• New core_interrupt, external_interrupt, and exception macros for defining interrupt and exception handlers
• New u-boot feature to execute U-boot binaries.