Skip to content

Fix uses of invalid LLVM intrinsics #1807

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 5 commits into from
May 30, 2025
Merged

Fix uses of invalid LLVM intrinsics #1807

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
5 commits
Select commit Hold shift + click to select a range
8b1c5b0
Fix `ldpte` and `lddir` signature
sayantn May 27, 2025
825e559
Fix PPC shift and rotate intrinsics
sayantn May 27, 2025
0c08e25
Fix s390x intrinsics
sayantn May 27, 2025
74e454d
Use the new definition of `rdtscp` intrinsic
sayantn May 27, 2025
06a170b
Upgrade more intrinsics to the new version
sayantn May 28, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
2 changes: 1 addition & 1 deletion ci/run.sh
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -10,7 +10,7 @@ set -ex
#export RUST_TEST_NOCAPTURE=1
#export RUST_TEST_THREADS=1

export RUSTFLAGS="${RUSTFLAGS} -D warnings -Z merge-functions=disabled "
export RUSTFLAGS="${RUSTFLAGS} -D warnings -Z merge-functions=disabled -Z verify-llvm-ir"
export HOST_RUSTFLAGS="${RUSTFLAGS}"
export PROFILE="${PROFILE:="--profile=release"}"

Expand Down
8 changes: 4 additions & 4 deletions crates/core_arch/src/aarch64/neon/generated.rs
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -21420,7 +21420,7 @@ pub fn vrbit_s8(a: int8x8_t) -> int8x8_t {
unsafe extern "unadjusted" {
#[cfg_attr(
any(target_arch = "aarch64", target_arch = "arm64ec"),
link_name = "llvm.aarch64.neon.rbit.v8i8"
link_name = "llvm.bitreverse.v8i8"
Copy link
Member

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Note to self: change these in cg_clif once this PR merges and rust-lang/rust updates stdarch.

)]
fn _vrbit_s8(a: int8x8_t) -> int8x8_t;
}
Expand All @@ -21436,7 +21436,7 @@ pub fn vrbitq_s8(a: int8x16_t) -> int8x16_t {
unsafe extern "unadjusted" {
#[cfg_attr(
any(target_arch = "aarch64", target_arch = "arm64ec"),
link_name = "llvm.aarch64.neon.rbit.v16i8"
link_name = "llvm.bitreverse.v16i8"
)]
fn _vrbitq_s8(a: int8x16_t) -> int8x16_t;
}
Expand Down Expand Up @@ -23871,7 +23871,7 @@ pub fn vrndn_f64(a: float64x1_t) -> float64x1_t {
unsafe extern "unadjusted" {
#[cfg_attr(
any(target_arch = "aarch64", target_arch = "arm64ec"),
link_name = "llvm.aarch64.neon.frintn.v1f64"
link_name = "llvm.roundeven.v1f64"
)]
fn _vrndn_f64(a: float64x1_t) -> float64x1_t;
}
Expand All @@ -23887,7 +23887,7 @@ pub fn vrndnq_f64(a: float64x2_t) -> float64x2_t {
unsafe extern "unadjusted" {
#[cfg_attr(
any(target_arch = "aarch64", target_arch = "arm64ec"),
link_name = "llvm.aarch64.neon.frintn.v2f64"
link_name = "llvm.roundeven.v2f64"
)]
fn _vrndnq_f64(a: float64x2_t) -> float64x2_t;
}
Expand Down
36 changes: 32 additions & 4 deletions crates/core_arch/src/arm_shared/neon/generated.rs
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -204,6 +204,7 @@ pub fn __crc32w(crc: u32, data: u32) -> u32 {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadal_s8)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg(target_arch = "arm")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s8"))]
#[cfg_attr(
Expand All @@ -221,6 +222,7 @@ fn priv_vpadal_s8(a: int16x4_t, b: int8x8_t) -> int16x4_t {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadalq_s8)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg(target_arch = "arm")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s8"))]
#[cfg_attr(
Expand All @@ -238,6 +240,7 @@ fn priv_vpadalq_s8(a: int16x8_t, b: int8x16_t) -> int16x8_t {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadal_s16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg(target_arch = "arm")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s16"))]
#[cfg_attr(
Expand All @@ -255,6 +258,7 @@ fn priv_vpadal_s16(a: int32x2_t, b: int16x4_t) -> int32x2_t {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadalq_s16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg(target_arch = "arm")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s16"))]
#[cfg_attr(
Expand All @@ -272,6 +276,7 @@ fn priv_vpadalq_s16(a: int32x4_t, b: int16x8_t) -> int32x4_t {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadal_s32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg(target_arch = "arm")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s32"))]
#[cfg_attr(
Expand All @@ -289,6 +294,7 @@ fn priv_vpadal_s32(a: int64x1_t, b: int32x2_t) -> int64x1_t {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadalq_s32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg(target_arch = "arm")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s32"))]
#[cfg_attr(
Expand All @@ -306,6 +312,7 @@ fn priv_vpadalq_s32(a: int64x2_t, b: int32x4_t) -> int64x2_t {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadal_u8)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg(target_arch = "arm")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u8"))]
#[cfg_attr(
Expand All @@ -323,6 +330,7 @@ fn priv_vpadal_u8(a: uint16x4_t, b: uint8x8_t) -> uint16x4_t {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadalq_u8)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg(target_arch = "arm")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u8"))]
#[cfg_attr(
Expand All @@ -340,6 +348,7 @@ fn priv_vpadalq_u8(a: uint16x8_t, b: uint8x16_t) -> uint16x8_t {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadal_u16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg(target_arch = "arm")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u16"))]
#[cfg_attr(
Expand All @@ -357,6 +366,7 @@ fn priv_vpadal_u16(a: uint32x2_t, b: uint16x4_t) -> uint32x2_t {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadalq_u16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg(target_arch = "arm")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u16"))]
#[cfg_attr(
Expand All @@ -374,6 +384,7 @@ fn priv_vpadalq_u16(a: uint32x4_t, b: uint16x8_t) -> uint32x4_t {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadal_u32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg(target_arch = "arm")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u32"))]
#[cfg_attr(
Expand All @@ -391,6 +402,7 @@ fn priv_vpadal_u32(a: uint64x1_t, b: uint32x2_t) -> uint64x1_t {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadalq_u32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg(target_arch = "arm")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u32"))]
#[cfg_attr(
Expand Down Expand Up @@ -58712,7 +58724,7 @@ pub fn vrndn_f16(a: float16x4_t) -> float16x4_t {
unsafe extern "unadjusted" {
#[cfg_attr(
any(target_arch = "aarch64", target_arch = "arm64ec"),
link_name = "llvm.aarch64.neon.frintn.v4f16"
link_name = "llvm.roundeven.v4f16"
)]
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrintn.v4f16")]
fn _vrndn_f16(a: float16x4_t) -> float16x4_t;
Expand All @@ -58734,7 +58746,7 @@ pub fn vrndnq_f16(a: float16x8_t) -> float16x8_t {
unsafe extern "unadjusted" {
#[cfg_attr(
any(target_arch = "aarch64", target_arch = "arm64ec"),
link_name = "llvm.aarch64.neon.frintn.v8f16"
link_name = "llvm.roundeven.v8f16"
)]
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrintn.v8f16")]
fn _vrndnq_f16(a: float16x8_t) -> float16x8_t;
Expand Down Expand Up @@ -58763,7 +58775,7 @@ pub fn vrndn_f32(a: float32x2_t) -> float32x2_t {
unsafe extern "unadjusted" {
#[cfg_attr(
any(target_arch = "aarch64", target_arch = "arm64ec"),
link_name = "llvm.aarch64.neon.frintn.v2f32"
link_name = "llvm.roundeven.v2f32"
)]
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrintn.v2f32")]
fn _vrndn_f32(a: float32x2_t) -> float32x2_t;
Expand Down Expand Up @@ -58792,7 +58804,7 @@ pub fn vrndnq_f32(a: float32x4_t) -> float32x4_t {
unsafe extern "unadjusted" {
#[cfg_attr(
any(target_arch = "aarch64", target_arch = "arm64ec"),
link_name = "llvm.aarch64.neon.frintn.v4f32"
link_name = "llvm.roundeven.v4f32"
)]
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrintn.v4f32")]
fn _vrndnq_f32(a: float32x4_t) -> float32x4_t;
Expand Down Expand Up @@ -61531,6 +61543,8 @@ pub fn vsha256su1q_u32(tw0_3: uint32x4_t, w8_11: uint32x4_t, w12_15: uint32x4_t)
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftins_v16i8)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg(target_arch = "arm")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
fn vshiftins_v16i8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t {
unsafe extern "unadjusted" {
Expand All @@ -61543,6 +61557,8 @@ fn vshiftins_v16i8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftins_v1i64)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg(target_arch = "arm")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
fn vshiftins_v1i64(a: int64x1_t, b: int64x1_t, c: int64x1_t) -> int64x1_t {
unsafe extern "unadjusted" {
Expand All @@ -61555,6 +61571,8 @@ fn vshiftins_v1i64(a: int64x1_t, b: int64x1_t, c: int64x1_t) -> int64x1_t {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftins_v2i32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg(target_arch = "arm")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
fn vshiftins_v2i32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t {
unsafe extern "unadjusted" {
Expand All @@ -61567,6 +61585,8 @@ fn vshiftins_v2i32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftins_v2i64)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg(target_arch = "arm")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
fn vshiftins_v2i64(a: int64x2_t, b: int64x2_t, c: int64x2_t) -> int64x2_t {
unsafe extern "unadjusted" {
Expand All @@ -61579,6 +61599,8 @@ fn vshiftins_v2i64(a: int64x2_t, b: int64x2_t, c: int64x2_t) -> int64x2_t {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftins_v4i16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg(target_arch = "arm")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
fn vshiftins_v4i16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t {
unsafe extern "unadjusted" {
Expand All @@ -61591,6 +61613,8 @@ fn vshiftins_v4i16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftins_v4i32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg(target_arch = "arm")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
fn vshiftins_v4i32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t {
unsafe extern "unadjusted" {
Expand All @@ -61603,6 +61627,8 @@ fn vshiftins_v4i32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftins_v8i16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg(target_arch = "arm")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
fn vshiftins_v8i16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t {
unsafe extern "unadjusted" {
Expand All @@ -61615,6 +61641,8 @@ fn vshiftins_v8i16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftins_v8i8)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg(target_arch = "arm")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
fn vshiftins_v8i8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t {
unsafe extern "unadjusted" {
Expand Down
10 changes: 6 additions & 4 deletions crates/core_arch/src/loongarch64/mod.rs
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -329,16 +329,18 @@ pub unsafe fn asrtgt(a: i64, b: i64) {

/// Loads the page table directory entry
#[inline]
#[rustc_legacy_const_generics(1)]
#[unstable(feature = "stdarch_loongarch", issue = "117427")]
pub unsafe fn lddir(a: i64, b: i64) -> i64 {
__lddir(a, b)
pub unsafe fn lddir<const B: i64>(a: i64) -> i64 {
__lddir(a, B)
}

/// Loads the page table entry
#[inline]
#[rustc_legacy_const_generics(1)]
#[unstable(feature = "stdarch_loongarch", issue = "117427")]
pub unsafe fn ldpte(a: i64, b: i64) {
__ldpte(a, b)
pub unsafe fn ldpte<const B: i64>(a: i64) {
__ldpte(a, B)
}

/// Calculate the approximate single-precision result of 1.0 divided
Expand Down
18 changes: 9 additions & 9 deletions crates/core_arch/src/powerpc/altivec.rs
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -338,26 +338,26 @@ unsafe extern "C" {
#[link_name = "llvm.ppc.altivec.vlogefp"]
fn vlogefp(a: vector_float) -> vector_float;

#[link_name = "llvm.ppc.altivec.sll"]
#[link_name = "llvm.ppc.altivec.vsl"]
fn vsl(a: vector_signed_int, b: vector_signed_int) -> vector_signed_int;
#[link_name = "llvm.ppc.altivec.slo"]
#[link_name = "llvm.ppc.altivec.vslo"]
fn vslo(a: vector_signed_int, b: vector_signed_int) -> vector_signed_int;

#[link_name = "llvm.ppc.altivec.srab"]
#[link_name = "llvm.ppc.altivec.vsrab"]
fn vsrab(a: vector_signed_char, b: vector_unsigned_char) -> vector_signed_char;
#[link_name = "llvm.ppc.altivec.srah"]
#[link_name = "llvm.ppc.altivec.vsrah"]
fn vsrah(a: vector_signed_short, b: vector_unsigned_short) -> vector_signed_short;
#[link_name = "llvm.ppc.altivec.sraw"]
#[link_name = "llvm.ppc.altivec.vsraw"]
fn vsraw(a: vector_signed_int, b: vector_unsigned_int) -> vector_signed_int;

#[link_name = "llvm.ppc.altivec.srl"]
#[link_name = "llvm.ppc.altivec.vsr"]
fn vsr(a: vector_signed_int, b: vector_signed_int) -> vector_signed_int;
#[link_name = "llvm.ppc.altivec.sro"]
#[link_name = "llvm.ppc.altivec.vsro"]
fn vsro(a: vector_signed_int, b: vector_signed_int) -> vector_signed_int;

#[link_name = "llvm.ppc.altivec.slv"]
#[link_name = "llvm.ppc.altivec.vslv"]
fn vslv(a: vector_unsigned_char, b: vector_unsigned_char) -> vector_unsigned_char;
#[link_name = "llvm.ppc.altivec.srv"]
#[link_name = "llvm.ppc.altivec.vsrv"]
fn vsrv(a: vector_unsigned_char, b: vector_unsigned_char) -> vector_unsigned_char;

#[link_name = "llvm.fshl.v16i8"]
Expand Down
18 changes: 9 additions & 9 deletions crates/core_arch/src/s390x/vector.rs
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -174,9 +174,9 @@ unsafe extern "unadjusted" {
#[link_name = "llvm.s390.vpklsfs"] fn vpklsfs(a: vector_unsigned_int, b: vector_unsigned_int) -> PackedTuple<vector_unsigned_short, i32>;
#[link_name = "llvm.s390.vpklsgs"] fn vpklsgs(a: vector_unsigned_long_long, b: vector_unsigned_long_long) -> PackedTuple<vector_unsigned_int, i32>;

#[link_name = "llvm.s390.vuplbw"] fn vuplbw (a: vector_signed_char) -> vector_signed_short;
#[link_name = "llvm.s390.vuplb"] fn vuplb (a: vector_signed_char) -> vector_signed_short;
#[link_name = "llvm.s390.vuplhw"] fn vuplhw (a: vector_signed_short) -> vector_signed_int;
#[link_name = "llvm.s390.vuplfw"] fn vuplfw (a: vector_signed_int) -> vector_signed_long_long;
#[link_name = "llvm.s390.vuplf"] fn vuplf (a: vector_signed_int) -> vector_signed_long_long;
#[link_name = "llvm.s390.vupllb"] fn vupllb (a: vector_unsigned_char) -> vector_unsigned_short;
#[link_name = "llvm.s390.vupllh"] fn vupllh (a: vector_unsigned_short) -> vector_unsigned_int;
#[link_name = "llvm.s390.vupllf"] fn vupllf (a: vector_unsigned_int) -> vector_unsigned_long_long;
Expand Down Expand Up @@ -2581,9 +2581,9 @@ mod sealed {
// FIXME(llvm): a shuffle + simd_as does not currently optimize into a single instruction like
// unpachk above. Tracked in https://github.com/llvm/llvm-project/issues/129576.

impl_vec_trait! {[VectorUnpackl vec_unpackl] vuplbw (vector_signed_char) -> vector_signed_short}
impl_vec_trait! {[VectorUnpackl vec_unpackl] vuplb (vector_signed_char) -> vector_signed_short}
impl_vec_trait! {[VectorUnpackl vec_unpackl] vuplhw (vector_signed_short) -> vector_signed_int}
impl_vec_trait! {[VectorUnpackl vec_unpackl] vuplfw (vector_signed_int) -> vector_signed_long_long}
impl_vec_trait! {[VectorUnpackl vec_unpackl] vuplf (vector_signed_int) -> vector_signed_long_long}

impl_vec_trait! {[VectorUnpackl vec_unpackl] vupllb (vector_unsigned_char) -> vector_unsigned_short}
impl_vec_trait! {[VectorUnpackl vec_unpackl] vupllh (vector_unsigned_short) -> vector_unsigned_int}
Expand Down Expand Up @@ -3011,9 +3011,9 @@ mod sealed {
#[inline]
#[target_feature(enable = "vector")]
unsafe fn vec_sel(self, b: Self, c: t_u!($ty)) -> Self {
let b = simd_and(b, transmute(c));
let a = simd_and(self, simd_xor(transmute(c), transmute(vector_signed_char([!0; 16]))));
simd_or(a, b)
let b = simd_and(transmute(b), c);
let a = simd_and(transmute(self), simd_xor(c, transmute(vector_signed_char([!0; 16]))));
transmute(simd_or(a, b))
}
}

Expand Down Expand Up @@ -3198,14 +3198,14 @@ mod sealed {
#[unstable(feature = "stdarch_s390x", issue = "135681")]
impl VectorSearchString for $ty {
#[inline]
#[target_feature(enable = "vector")]
#[target_feature(enable = "vector-enhancements-2")]
unsafe fn vec_search_string_cc(self, b: Self, c: vector_unsigned_char) -> (vector_unsigned_char, i32) {
let PackedTuple { x,y } = $intr_s(transmute(self), transmute(b), c);
(x, y)
}

#[inline]
#[target_feature(enable = "vector")]
#[target_feature(enable = "vector-enhancements-2")]
unsafe fn vec_search_string_until_zero_cc(self, b: Self, c: vector_unsigned_char) -> (vector_unsigned_char, i32) {
let PackedTuple { x,y } = $intr_sz(transmute(self), transmute(b), c);
(x, y)
Expand Down
4 changes: 2 additions & 2 deletions crates/core_arch/src/x86/avx.rs
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -573,7 +573,7 @@ pub fn _mm256_blendv_ps(a: __m256, b: __m256, c: __m256) -> __m256 {
#[stable(feature = "simd_x86", since = "1.27.0")]
pub fn _mm256_dp_ps<const IMM8: i32>(a: __m256, b: __m256) -> __m256 {
static_assert_uimm_bits!(IMM8, 8);
unsafe { vdpps(a, b, IMM8) }
unsafe { vdpps(a, b, IMM8 as i8) }
}

/// Horizontal addition of adjacent pairs in the two packed vectors
Expand Down Expand Up @@ -3043,7 +3043,7 @@ unsafe extern "C" {
#[link_name = "llvm.x86.avx.round.ps.256"]
fn roundps256(a: __m256, b: i32) -> __m256;
#[link_name = "llvm.x86.avx.dp.ps.256"]
fn vdpps(a: __m256, b: __m256, imm8: i32) -> __m256;
fn vdpps(a: __m256, b: __m256, imm8: i8) -> __m256;
#[link_name = "llvm.x86.avx.hadd.pd.256"]
fn vhaddpd(a: __m256d, b: __m256d) -> __m256d;
#[link_name = "llvm.x86.avx.hadd.ps.256"]
Expand Down
Loading