platforms.yml: fix RISC-V march

[Ivan-Velickovic]

I think this is only used for the name of the CI job and nothing else. Now that the kernel defaults to FPU support on for RISC-V, we should probably change all of these to reflect that.

[lsf37]

It turns out there are lots of mentions of this still in various workflows (21 if I counted correctly). We need to update those simultaneously. Most of these are from invocations of the sel4test and sel4bench tests, which I could point to the factored out workflow in this repo now. I've trialled this in the seL4 repo and it has been working fairly well there.

The other ones are deployment workflows in seL4, sel4test, sel4bench, various mentions in the ci-action repo, and the simulation workflows for PRs. The simulation workflow also has a factored out version here, but the repos still need to be updated.

So overall, if everything is updated to point to the factored out workflows, it should be feasible to find all mentions.

Once that is done, we could remove march completely and either introduce some other ID that jobs are split by our do the matrix split differently.

[lsf37]

There are also still 3 mentions of rv64imac in various dts files in the seL4 repo:

tools/dts/star64.dts
201:			riscv,isa = "rv64imac";

tools/dts/hifive.dts
35:      riscv,isa = "rv64imac";

tools/dts/mpfs_icicle.dts
23:			riscv,isa = "rv64imac";

[lsf37]

Not really relevant for the setting here, but not clear to me if they need to be updated or not now that we have switched to a different default. We are still on rv64imac for verification, though.

[Ivan-Velickovic]

There are also still 3 mentions of rv64imac in various dts files in the seL4 repo:

tools/dts/star64.dts
201:			riscv,isa = "rv64imac";

tools/dts/hifive.dts
35:      riscv,isa = "rv64imac";

tools/dts/mpfs_icicle.dts
23:			riscv,isa = "rv64imac";

Those are all referring to the ISA of an extra 'supervisor core' on those platforms from memory. seL4 does not run on those cores.