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This is sifive's public fork of Testchipip. Changes required by parent repositiories should be made against the sifive branch.

testchipip

Useful IP components for chips. BAR projects generally use these components with rocket-chip.

Blocks

  • Block device model
  • Clock utilities for Chisel, e.g. clock mux, clock divider, etc.
  • SERDES <-> TileLink
  • Custom serial interface for debug with simulator interface
  • TileLink splitter, switcher

Usage

Testchipip can be used in your project in one of two ways:

  1. As an sbt subproject that depends on rocket-chip, as in chipyard
  2. As a maven dependency (e.g. write
libraryDependencies += "edu.berkeley.cs" %% "testchipip" % "1.0-020719-SNAPSHOT"

in your build.sbt). Check sonatype to see the latest published version.

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  • Scala 69.5%
  • C++ 14.9%
  • Verilog 6.9%
  • SystemVerilog 5.2%
  • Shell 2.2%
  • Assembly 0.8%
  • Makefile 0.5%