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allow coexistence of ethernet and IO link for ASIC designs (#183)
-changes to I/O tile to allow both iolink and Ethernet -add new ahbslv2iolink proxy to drive iolink from Ethernet master -new dual-FPGA setup for esp_asic_generic that supports iolink control and memory access from an FPGA proxy Co-authored-by: biruk <[email protected]>
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| # Copyright (c) 2011-2021 Columbia University, System Level Design Group | ||
| # SPDX-License-Identifier: Apache-2.0 | ||
| # FPGA and Dev Board used in Design | ||
| PART=XC7V2000T | ||
| PACKAGE=flg1925 | ||
| SPEED=2 |
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| <?xml version="1.0" encoding="UTF-8" standalone="no" ?> | ||
| <Project NoOfControllers="1"> | ||
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| <!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. --> | ||
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| <ModuleName>mig</ModuleName> | ||
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| <dci_inouts_inputs>1</dci_inouts_inputs> | ||
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| <dci_inputs>1</dci_inputs> | ||
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| <Debug_En>OFF</Debug_En> | ||
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| <DataDepth_En>1024</DataDepth_En> | ||
|
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| <LowPower_En>OFF</LowPower_En> | ||
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| <XADC_En>Enabled</XADC_En> | ||
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| <TargetFPGA>xc7v2000t-flg1925/-2</TargetFPGA> | ||
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| <Version>4.2</Version> | ||
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| <SystemClock>Differential</SystemClock> | ||
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| <ReferenceClock>Differential</ReferenceClock> | ||
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| <SysResetPolarity>ACTIVE LOW</SysResetPolarity> | ||
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| <BankSelectionFlag>FALSE</BankSelectionFlag> | ||
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| <InternalVref>0</InternalVref> | ||
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| <dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs> | ||
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| <dci_cascade>1</dci_cascade> | ||
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| <Controller number="0"> | ||
| <MemoryDevice>DDR3_SDRAM/Components/MT41J256m16XX-125</MemoryDevice> | ||
| <TimePeriod>2500</TimePeriod> | ||
| <VccAuxIO>1.8V</VccAuxIO> | ||
| <PHYRatio>4:1</PHYRatio> | ||
| <InputClkFreq>200</InputClkFreq> | ||
| <UIExtraClocks>0</UIExtraClocks> | ||
| <MMCM_VCO>800</MMCM_VCO> | ||
| <MMCMClkOut0> 1.000</MMCMClkOut0> | ||
| <MMCMClkOut1>1</MMCMClkOut1> | ||
| <MMCMClkOut2>1</MMCMClkOut2> | ||
| <MMCMClkOut3>1</MMCMClkOut3> | ||
| <MMCMClkOut4>1</MMCMClkOut4> | ||
| <DataWidth>64</DataWidth> | ||
| <DeepMemory>1</DeepMemory> | ||
| <DataMask>1</DataMask> | ||
| <ECC>Disabled</ECC> | ||
| <Ordering>Strict</Ordering> | ||
| <BankMachineCnt>4</BankMachineCnt> | ||
| <CustomPart>FALSE</CustomPart> | ||
| <NewPartName/> | ||
| <RowAddress>15</RowAddress> | ||
| <ColAddress>10</ColAddress> | ||
| <BankAddress>3</BankAddress> | ||
| <MemoryVoltage>1.5V</MemoryVoltage> | ||
| <UserMemoryAddressMap>BANK_ROW_COLUMN</UserMemoryAddressMap> | ||
| <PinSelection> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AT37" SLEW="" VCCAUX_IO="" name="calib_complete"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AN41" SLEW="" VCCAUX_IO="" name="ddr3_addr[0]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AP38" SLEW="" VCCAUX_IO="" name="ddr3_addr[10]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AN38" SLEW="" VCCAUX_IO="" name="ddr3_addr[11]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AN37" SLEW="" VCCAUX_IO="" name="ddr3_addr[12]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AR38" SLEW="" VCCAUX_IO="" name="ddr3_addr[13]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AR37" SLEW="" VCCAUX_IO="" name="ddr3_addr[14]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AP44" SLEW="" VCCAUX_IO="" name="ddr3_addr[1]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AP43" SLEW="" VCCAUX_IO="" name="ddr3_addr[2]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AP40" SLEW="" VCCAUX_IO="" name="ddr3_addr[3]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AN39" SLEW="" VCCAUX_IO="" name="ddr3_addr[4]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AP36" SLEW="" VCCAUX_IO="" name="ddr3_addr[5]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AN36" SLEW="" VCCAUX_IO="" name="ddr3_addr[6]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AR36" SLEW="" VCCAUX_IO="" name="ddr3_addr[7]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AR35" SLEW="" VCCAUX_IO="" name="ddr3_addr[8]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AP39" SLEW="" VCCAUX_IO="" name="ddr3_addr[9]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AT43" SLEW="" VCCAUX_IO="" name="ddr3_ba[0]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AR43" SLEW="" VCCAUX_IO="" name="ddr3_ba[1]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AP41" SLEW="" VCCAUX_IO="" name="ddr3_ba[2]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AR41" SLEW="" VCCAUX_IO="" name="ddr3_cas_n"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AP35" SLEW="" VCCAUX_IO="" name="ddr3_ck_n[0]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AP34" SLEW="" VCCAUX_IO="" name="ddr3_ck_p[0]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AU41" SLEW="" VCCAUX_IO="" name="ddr3_cke[0]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AT42" SLEW="" VCCAUX_IO="" name="ddr3_cs_n[0]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AJ41" SLEW="" VCCAUX_IO="" name="ddr3_dm[0]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="BB41" SLEW="" VCCAUX_IO="" name="ddr3_dm[1]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AY36" SLEW="" VCCAUX_IO="" name="ddr3_dm[2]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AJ33" SLEW="" VCCAUX_IO="" name="ddr3_dm[3]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AW40" SLEW="" VCCAUX_IO="" name="ddr3_dm[4]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AH36" SLEW="" VCCAUX_IO="" name="ddr3_dm[5]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AL42" SLEW="" VCCAUX_IO="" name="ddr3_dm[6]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="BA34" SLEW="" VCCAUX_IO="" name="ddr3_dm[7]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AK41" SLEW="" VCCAUX_IO="" name="ddr3_dq[0]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="BD41" SLEW="" VCCAUX_IO="" name="ddr3_dq[10]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="BC39" SLEW="" VCCAUX_IO="" name="ddr3_dq[11]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="BD39" SLEW="" VCCAUX_IO="" name="ddr3_dq[12]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="BB39" SLEW="" VCCAUX_IO="" name="ddr3_dq[13]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="BB40" SLEW="" VCCAUX_IO="" name="ddr3_dq[14]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AY40" SLEW="" VCCAUX_IO="" name="ddr3_dq[15]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AY38" SLEW="" VCCAUX_IO="" name="ddr3_dq[16]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="BA39" SLEW="" VCCAUX_IO="" name="ddr3_dq[17]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="BA37" SLEW="" VCCAUX_IO="" name="ddr3_dq[18]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="BA38" SLEW="" VCCAUX_IO="" name="ddr3_dq[19]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AK40" SLEW="" VCCAUX_IO="" name="ddr3_dq[1]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AY37" SLEW="" VCCAUX_IO="" name="ddr3_dq[20]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="BC38" SLEW="" VCCAUX_IO="" name="ddr3_dq[21]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="BD38" SLEW="" VCCAUX_IO="" name="ddr3_dq[22]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="BB37" SLEW="" VCCAUX_IO="" name="ddr3_dq[23]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AL34" SLEW="" VCCAUX_IO="" name="ddr3_dq[24]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AM34" SLEW="" VCCAUX_IO="" name="ddr3_dq[25]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AL35" SLEW="" VCCAUX_IO="" name="ddr3_dq[26]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AM35" SLEW="" VCCAUX_IO="" name="ddr3_dq[27]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AJ35" SLEW="" VCCAUX_IO="" name="ddr3_dq[28]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AK35" SLEW="" VCCAUX_IO="" name="ddr3_dq[29]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AL40" SLEW="" VCCAUX_IO="" name="ddr3_dq[2]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AH32" SLEW="" VCCAUX_IO="" name="ddr3_dq[30]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AH33" SLEW="" VCCAUX_IO="" name="ddr3_dq[31]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AW41" SLEW="" VCCAUX_IO="" name="ddr3_dq[32]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AY43" SLEW="" VCCAUX_IO="" name="ddr3_dq[33]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="BA43" SLEW="" VCCAUX_IO="" name="ddr3_dq[34]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AY41" SLEW="" VCCAUX_IO="" name="ddr3_dq[35]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AY42" SLEW="" VCCAUX_IO="" name="ddr3_dq[36]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="BA44" SLEW="" VCCAUX_IO="" name="ddr3_dq[37]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="BB44" SLEW="" VCCAUX_IO="" name="ddr3_dq[38]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="BA42" SLEW="" VCCAUX_IO="" name="ddr3_dq[39]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AH43" SLEW="" VCCAUX_IO="" name="ddr3_dq[3]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AJ36" SLEW="" VCCAUX_IO="" name="ddr3_dq[40]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AH37" SLEW="" VCCAUX_IO="" name="ddr3_dq[41]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AH38" SLEW="" VCCAUX_IO="" name="ddr3_dq[42]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AJ38" SLEW="" VCCAUX_IO="" name="ddr3_dq[43]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AK38" SLEW="" VCCAUX_IO="" name="ddr3_dq[44]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AL37" SLEW="" VCCAUX_IO="" name="ddr3_dq[45]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AL38" SLEW="" VCCAUX_IO="" name="ddr3_dq[46]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AK36" SLEW="" VCCAUX_IO="" name="ddr3_dq[47]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AM40" SLEW="" VCCAUX_IO="" name="ddr3_dq[48]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AM41" SLEW="" VCCAUX_IO="" name="ddr3_dq[49]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AH44" SLEW="" VCCAUX_IO="" name="ddr3_dq[4]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AL39" SLEW="" VCCAUX_IO="" name="ddr3_dq[50]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AM39" SLEW="" VCCAUX_IO="" name="ddr3_dq[51]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AL43" SLEW="" VCCAUX_IO="" name="ddr3_dq[52]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AL44" SLEW="" VCCAUX_IO="" name="ddr3_dq[53]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AM44" SLEW="" VCCAUX_IO="" name="ddr3_dq[54]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AN43" SLEW="" VCCAUX_IO="" name="ddr3_dq[55]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="BC34" SLEW="" VCCAUX_IO="" name="ddr3_dq[56]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="BD34" SLEW="" VCCAUX_IO="" name="ddr3_dq[57]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="BB36" SLEW="" VCCAUX_IO="" name="ddr3_dq[58]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="BC36" SLEW="" VCCAUX_IO="" name="ddr3_dq[59]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AJ43" SLEW="" VCCAUX_IO="" name="ddr3_dq[5]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AW35" SLEW="" VCCAUX_IO="" name="ddr3_dq[60]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AY35" SLEW="" VCCAUX_IO="" name="ddr3_dq[61]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="BA35" SLEW="" VCCAUX_IO="" name="ddr3_dq[62]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="BB35" SLEW="" VCCAUX_IO="" name="ddr3_dq[63]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AJ44" SLEW="" VCCAUX_IO="" name="ddr3_dq[6]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AJ39" SLEW="" VCCAUX_IO="" name="ddr3_dq[7]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="BC41" SLEW="" VCCAUX_IO="" name="ddr3_dq[8]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="BD40" SLEW="" VCCAUX_IO="" name="ddr3_dq[9]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AK43" SLEW="" VCCAUX_IO="" name="ddr3_dqs_n[0]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="BC43" SLEW="" VCCAUX_IO="" name="ddr3_dqs_n[1]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AW39" SLEW="" VCCAUX_IO="" name="ddr3_dqs_n[2]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AL33" SLEW="" VCCAUX_IO="" name="ddr3_dqs_n[3]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AW44" SLEW="" VCCAUX_IO="" name="ddr3_dqs_n[4]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AM37" SLEW="" VCCAUX_IO="" name="ddr3_dqs_n[5]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AN42" SLEW="" VCCAUX_IO="" name="ddr3_dqs_n[6]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="BD36" SLEW="" VCCAUX_IO="" name="ddr3_dqs_n[7]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AK42" SLEW="" VCCAUX_IO="" name="ddr3_dqs_p[0]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="BC42" SLEW="" VCCAUX_IO="" name="ddr3_dqs_p[1]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AW38" SLEW="" VCCAUX_IO="" name="ddr3_dqs_p[2]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AK33" SLEW="" VCCAUX_IO="" name="ddr3_dqs_p[3]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AW43" SLEW="" VCCAUX_IO="" name="ddr3_dqs_p[4]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AM36" SLEW="" VCCAUX_IO="" name="ddr3_dqs_p[5]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AM42" SLEW="" VCCAUX_IO="" name="ddr3_dqs_p[6]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="BD35" SLEW="" VCCAUX_IO="" name="ddr3_dqs_p[7]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AV41" SLEW="" VCCAUX_IO="" name="ddr3_odt[0]"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AR40" SLEW="" VCCAUX_IO="" name="ddr3_ras_n"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="BC37" SLEW="" VCCAUX_IO="" name="ddr3_reset_n"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AR42" SLEW="" VCCAUX_IO="" name="ddr3_we_n"/> | ||
| <Pin IN_TERM="" IOSTANDARD="" PADName="AV34" SLEW="" VCCAUX_IO="" name="diagnostic_led"/> | ||
| </PinSelection> | ||
| <Reference_Clock> | ||
| <Pin Bank="14" PADName="AD41/AE41(CC_P/N)" name="clk_ref_p/n"/> | ||
| </Reference_Clock> | ||
| <System_Clock> | ||
| <Pin Bank="15" PADName="AC41/AB41(CC_P/N)" name="sys_clk_p/n"/> | ||
| </System_Clock> | ||
| <System_Control> | ||
| <Pin Bank="Select Bank" PADName="No connect" name="sys_rst"/> | ||
| <Pin Bank="Select Bank" PADName="No connect" name="init_calib_complete"/> | ||
| <Pin Bank="Select Bank" PADName="No connect" name="tg_compare_error"/> | ||
| </System_Control> | ||
| <TimingParameters> | ||
| <Parameters tcke="5" tfaw="40" tras="35" trcd="13.75" trefi="7.8" trfc="260" trp="13.75" trrd="7.5" trtp="7.5" twtr="7.5"/> | ||
| </TimingParameters> | ||
| <mrBurstLength name="Burst Length">8 - Fixed</mrBurstLength> | ||
| <mrBurstType name="Read Burst Type and Length">Sequential</mrBurstType> | ||
| <mrCasLatency name="CAS Latency">6</mrCasLatency> | ||
| <mrMode name="Mode">Normal</mrMode> | ||
| <mrDllReset name="DLL Reset">No</mrDllReset> | ||
| <mrPdMode name="DLL control for precharge PD">Slow Exit</mrPdMode> | ||
| <emrDllEnable name="DLL Enable">Enable</emrDllEnable> | ||
| <emrOutputDriveStrength name="Output Driver Impedance Control">RZQ/7</emrOutputDriveStrength> | ||
| <emrMirrorSelection name="Address Mirroring">Disable</emrMirrorSelection> | ||
| <emrCSSelection name="Controller Chip Select Pin">Enable</emrCSSelection> | ||
| <emrRTT name="RTT (nominal) - On Die Termination (ODT)">RZQ/4</emrRTT> | ||
| <emrPosted name="Additive Latency (AL)">0</emrPosted> | ||
| <emrOCD name="Write Leveling Enable">Disabled</emrOCD> | ||
| <emrDQS name="TDQS enable">Enabled</emrDQS> | ||
| <emrRDQS name="Qoff">Output Buffer Enabled</emrRDQS> | ||
| <mr2PartialArraySelfRefresh name="Partial-Array Self Refresh">Full Array</mr2PartialArraySelfRefresh> | ||
| <mr2CasWriteLatency name="CAS write latency">5</mr2CasWriteLatency> | ||
| <mr2AutoSelfRefresh name="Auto Self Refresh">Enabled</mr2AutoSelfRefresh> | ||
| <mr2SelfRefreshTempRange name="High Temparature Self Refresh Rate">Normal</mr2SelfRefreshTempRange> | ||
| <mr2RTTWR name="RTT_WR - Dynamic On Die Termination (ODT)">Dynamic ODT off</mr2RTTWR> | ||
| <PortInterface>NATIVE</PortInterface> | ||
| </Controller> | ||
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| </Project> |
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