init anon repo

slh-dsa · Feb 13, 2024 · bc32fcb · bc32fcb
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diff --git a/LICENSE b/LICENSE
@@ -0,0 +1,21 @@
+MIT License
+
+Copyright (c) 2024 ((Anonymous))
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
diff --git a/Makefile b/Makefile
@@ -0,0 +1,133 @@
+#	Makefile
+#	((Anonymized.))  See LICENSE.
+
+#	target
+PROJ	=	sloth
+BUILD	=	_build
+PROF	=	_prof
+
+#	rtl
+RTL		=	$(wildcard rtl/*.v)
+VFLAGS	=	-Irtl
+VVP		=	$(BUILD)/$(PROJ).vvp
+PC_LOG	=	core_pc.log
+
+#	cross compiler
+FW		?=	firmware
+CCONF_H	?=	config.h
+XCHAIN	?= 	riscv64-unknown-elf-
+CFLAGS	= 	-O2 -Wall -g -mabi=ilp32 -march=rv32imc
+CFLAGS	+=	-include $(CCONF_H) -DNDEBUG
+LDFLAGS	= 	-Wl,-Bstatic,-T,flow/riscv.ld,--no-relax
+KATNUM	?=	10
+CFLAGS	+=	-DKATNUM=$(KATNUM)
+
+#	firmware sources
+CSRC	+=	$(wildcard drv/*.c slh/*.c)
+SSRC	+=	$(wildcard drv/*.S)
+OBJS	+=	$(CSRC:.c=.o) $(SSRC:.S=.o)
+CFLAGS	+=	-Idrv -Islh
+
+#	default target
+
+all:	veri
+prof:	$(PROF)/func.txt
+
+#	verilator
+
+veri:	$(BUILD)/Vsim_tb $(FW).hex
+	./$(BUILD)/Vsim_tb
+
+$(BUILD)/Vsim_tb: $(BUILD)/Vsim_tb.mk
+	cd $(BUILD) && $(MAKE) -f Vsim_tb.mk CC=gcc LDFLAGS=""
+
+$(BUILD)/Vsim_tb.mk: $(RTL) flow/sim_tb.cpp
+	verilator $(VFLAGS) -Mdir $(BUILD) -cc --exe \
+		--top-module sim_tb -DSIM_TB $(RTL) flow/sim_tb.cpp
+
+#	icarus verilog
+
+sim:	$(VVP)
+	vvp -N $(VVP)
+
+$(VVP):	$(BUILD) $(RTL) $(FW).hex
+	iverilog $(VFLAGS) -DSIM_TB -o $(VVP) $(RTL)
+
+#	get firmware configuration from config.vh
+
+$(CCONF_H):	rtl/config.vh
+	cat $^ | tr '`' '#' | \
+		grep -vi -e "#timescale" -e "#default_nettype" > $(CCONF_H)
+
+#	fpga
+
+cw305.bit: $(BUILD) $(RTL) $(FW).hex
+	cp $(FW).hex $(BUILD)
+	cd $(BUILD) && $(VIVADO)vivado -mode batch \
+		-log cw305_synth.log -source ../flow/xc7a100t-synth.tcl
+
+vcu118.bit: $(BUILD) $(RTL) $(FW).hex
+	cp $(FW).hex $(BUILD)
+	cd $(BUILD) && $(VIVADO)vivado -mode batch \
+		-log vcu118_synth.log -source ../flow/xcvu9p-synth.tcl
+
+#	asic synth
+
+synth:
+	cd flow/yosys-syn && $(MAKE) synth
+
+#	program using the chipwhisperer interface
+
+cw305_prog:	cw305.bit
+	python3 flow/prog_cw305.py
+
+bits:	cw305.bit
+prog:	cw305_prog
+
+#	build firmware
+
+$(FW).elf:	$(OBJS)
+	$(XCHAIN)gcc $(LDFLAGS) $(CFLAGS)  $(OBJS)	-o $@ $(LIBS)
+	$(XCHAIN)size -t $(OBJS) 
+	$(XCHAIN)size -t $(FW).elf
+
+%.o: %.c $(CCONF_H)
+	$(XCHAIN)gcc $(CFLAGS) -c -o $@ $<
+
+%.o: %.S $(CCONF_H)
+	$(XCHAIN)gcc $(CFLAGS) -c -o $@ $<
+
+$(FW).dis:	$(FW).elf
+	$(XCHAIN)objdump -g -d -l -S --source-comment='#' $^ > $@
+
+$(FW).bin:	$(CCONF_H) $(FW).elf $(CSRC)
+	$(XCHAIN)objcopy -O binary $(FW).elf $@
+
+$(FW).hex:	$(FW).bin
+	hexdump -v -e '1/4 "%08x\n"' $^ > $@
+
+#	profiling with the program counter log
+#	requires CORE_PC_LOG macro to be manually set in verilator!
+
+$(PC_LOG):	veri
+
+$(FW).pmap:	$(PC_LOG) $(FW).elf $(BUILD)
+	$(XCHAIN)addr2line  -a -C -f -i -e $(FW).elf < $(PC_LOG) > $@
+
+$(PROF)/func.txt:	$(FW).pmap
+	rm -rf $(PROF)
+	mkdir $(PROF)
+	cd $(PROF) && ../flow/eprof.py
+
+#	cleanup
+
+$(BUILD):
+	mkdir -p $(BUILD)
+
+clean:
+	$(RM)	-f	$(FW).* $(CCONF_H) $(OBJS) $(VVP) 
+	$(RM)	-rf $(PROF) $(BUILD)
+	$(RM)	-f	*.jou *.log *.bit
+	cd slh && $(MAKE) clean
+	cd flow/yosys-syn && $(MAKE) clean
+
diff --git a/README.md b/README.md
@@ -0,0 +1,104 @@
+v#       SLotH
+
+An accelerator / codesign for SLH-DSA ("Stateless Hash-Based Digital Signature Standard") as described in [FIPS 205 Initial Public Draft](https://doi.org/10.6028/NIST.FIPS.205.ipd) from August 2023. 
+
+To cite this work, please use:
+```
+@misc{sa24sloth,
+    author          = {anon},
+    title           = {{SLotH}: Accelerating SLH-DSA by Two Orders of Magnitude},
+    howpublished    = {{IACR} ePrint 2024/0000},
+    url             = {https://eprint.iacr.org/2024/0000},
+    year            = {2024}
+}
+```
+
+To clone the repository:
+```
+git clone ((Anonymized.))
+```
+
+Directory structure
+```
+sloth
+├── slh             # Self-Contained C Implementation of SLH-DSA
+├── rtl             # Verilog HDL source code
+├── drv             # Accelerator drivers and test code
+├── kat             # SLH-DSA Known Answer Test data
+├── flow            # Misc files for FPGA and ASIC flows
+├── Makefile        # Convenience Makefile for the Accelerator
+├── LICENSE
+└── README.md
+```
+
+##      Core Algorithm in ANSI C
+
+The SLotH accelerator uses a core SLH-DSA algorithm implementation contained in the
+[slh](slh) directory. The core implementation is self-contained ANSI C code and should be able to run on pretty much any target. There are no prerequisites except for `make` and a C compiler.
+```
+cd sloth/slh
+make test
+```
+See [slh/README.md](slh/README.md) for more information.
+
+
+##      Verilator Simulation
+
+As a prerequisite for simulation, you'll need:
+
+*	[Verilator](https://github.com/verilator/verilator) verilog simulator.
+*	A RISC-V cross-compiler that supports bare-metal targets. You can build a suitable [riscv-gnu-toolchain](https://github.com/riscv/riscv-gnu-toolchain) 
+with `./configure --enable-multilib` and `make newlib`. 
+
+Both of these may be available as packages for Linux operating systems. The name of your toolchain is set in `XCHAIN` variable in the [Makefile](Makefile).
+
+To build and run a quick end-to-end test, try:
+```
+make veri
+```
+After a successful compilation the output should look something like this:
+```
+./_build/Vsim_tb
+
+[RESET]    ______        __  __ __
+          / __/ /  ___  / /_/ // /  SLotH Accelerator Test 2024/02
+         _\ \/ /__/ _ \/ __/ _  /   SLH-DSA / FIPS 205 ipd
+        /___/____/\___/\__/_//_/    ((Anonymized.))
+
+[INFO]  === Basic health test ===
+[CLK]   778     sha256_compress()
+[PASS]  sha256 ( chk= 55F39AFA )
+[CLK]   1460    sha512_compress()
+[PASS]  sha512 ( chk= 1F59A287 )
+[CLK]   1469    keccak_f1600()
+[PASS]  shake256 ( chk= 07C97065 )
+
+[INFO]  === Timing / KAT === 
+[INFO]  SLH-DSA-SHAKE-128f
+[INFO]  kat test count = 0
+[CLK]   SLH-DSA-SHAKE-128f 202180 slh_keygen()
+[STK]   SLH-DSA-SHAKE-128f 3156 slh_keygen()
+[PASS]  sk ( chk= BCA6B2C3 )
+[CLK]   SLH-DSA-SHAKE-128f 4923932 slh_sign()
+[STK]   SLH-DSA-SHAKE-128f 3940 slh_sign()
+[PASS]  sm ( chk= C03DA016 )
+[CLK]   SLH-DSA-SHAKE-128f 438901 slh_verify()
+[STK]   SLH-DSA-SHAKE-128f 3284 slh_verify()
+[PASS]  slh_verify() flip bit = 12389
+[PASS]  All tests ok.
+
+You can press key. Press x to exit.
+UART 0x78 x
+
+
+exit()
+
+[**TRAP**]    8145868
+- rtl/sim_tb.v:36: Verilog $finish
+```
+The readout from this particular execution of SLH-DSA-SHAKE-128f is that KeyGen was 202180 cycles, signing was 4923932 cycles, and verification was 438901 cycles. Furthermore, the self-tests were a PASS; the output matched the Known Answer Tests.
+
+
+##	Side-Channel Collection
+
+I collect traces from the 20dB low amplified SMA connector (X4). Bit 0 of the GPIO register connects to the SMA connector T13 "CLKOUT" on the board, and this is used as a trigger by `test_leak.c`. The trace collection and analysis stuff is not included, and anyway works only with my oscilloscope.