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sg200x: trm: fixed clk_187p5m issue #142

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Oct 28, 2024
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sg200x: trm: fixed clk_187p5m issue #142

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4 changes: 1 addition & 3 deletions SG200X/TRM/contents/cn/clock/div_crg_registers_description.table.rst
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Original file line number Diff line number Diff line change
Expand Up @@ -189,9 +189,7 @@ clk_en_1
| | | | clk_apb_spi3 (1: | |
| | | | Enable; 0: Gate) | |
+------+----------------------+-------+------------------------+------+
| 13 | clk_en_1_13 | R/W | Clock Enable for | 0x1 |
| | | | clk_187p5m (1: Enable; | |
| | | | 0: Gate) | |
| 13 | clk_en_1_13 | R/W | Resvered | 0x1 |
+------+----------------------+-------+------------------------+------+
| 14 | clk_en_1_14 | R/W | Clock Enable for | 0x1 |
| | | | clk_uart0 (1: Enable; | |
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2 changes: 1 addition & 1 deletion SG200X/TRM/contents/cn/peripherals/uart.rst
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Expand Up @@ -118,7 +118,7 @@ UART 是一普遍通用之点对点物理层传输协议，可以用来对接各

- UART 工作时钟 (UART_SCLK) 配置

可参考 CLK_DIV CRG 寄存器描述，配置 clk_sel_0_9~ clk_sel_0_13 选择 uart0~uart4 的工作时钟。预设为 1: XTAL 25MHz，配置为 0 即选择 UART PLL 分频时钟源。 PLL 分频时钟源预设为 187.5MHz ，若有需要可以配置分频寄存器 div_clk_187p5m 调整 PLL 分频时钟为 1500/NMHz，最高达 187.5MHz。
可参考 CLK_DIV CRG 寄存器描述，配置 clk_sel_0_9~ clk_sel_0_13 选择 uart0~uart4 的工作时钟。预设为 1: XTAL 25MHz，配置为 0 即选择 UART PLL 分频时钟源。 PLL 分频时钟源预设为 187.5MHz ，若有需要可以配置分频寄存器 div_clk_cam0_200 调整 PLL 分频时钟为 1500/NMHz，最高达 187.5MHz。

- UART 波特率配置

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2 changes: 1 addition & 1 deletion SG200X/TRM/contents/en/peripherals/uart.rst
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Expand Up @@ -118,7 +118,7 @@ Baud Rate Configuration

- UART working clock (UART_SCLK) configuration

You can refer to the CLK_DIV CRG register description to configure clk_sel_0_9~ clk_sel_0_13 to select the working clock of uart0~uart4. The default is 1: XTAL 25MHz. If configured as 0, the UART PLL divided clock source is selected. The PLL frequency division clock source is preset to 187.5MHz. If necessary, you can configure the frequency division register div_clk_187p5m to adjust the PLL frequency division clock to 1500/NMHz, up to 187.5MHz.
You can refer to the CLK_DIV CRG register description to configure clk_sel_0_9~ clk_sel_0_13 to select the working clock of uart0~uart4. The default is 1: XTAL 25MHz. If configured as 0, the UART PLL divided clock source is selected. The PLL frequency division clock source is preset to 187.5MHz. If necessary, you can configure the frequency division register div_clk_cam0_200 to adjust the PLL frequency division clock to 1500/NMHz, up to 187.5MHz.

- UART baud rate configuration

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