stm32-rs: 0.14.0 -> 0.15.1

stm32-rs · Jul 4, 2022 · 15574db · 15574db
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commit 15574db
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diff --git a/CHANGELOG.md b/CHANGELOG.md
@@ -14,6 +14,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 
 ## Changed
 - `Rtc.alarm_{a,b}` returns `Alarm` instead of `Option<Alarm>`.
+- Updated `stm32-rs` from `0.14.0` to `0.15.1`.
 
 ### Fixed
 - Fixed a documentation bug in `rtc::Alarm`.  Values are masked if `true`, but the documentation indicated they are masked if `false`.

diff --git a/Cargo.lock b/Cargo.lock
diff --git a/hal/Cargo.toml b/hal/Cargo.toml
@@ -38,7 +38,7 @@ num-traits = { version = "0.2", default-features = false }
 num-integer = { version = "0.1", default-features = false }
 paste = "1"
 rand_core = "0.6"
-stm32wl = { version = "0.14", default-features = false }
+stm32wl = { version = "0.15.1", default-features = false }
 void = { version = "1", default-features = false }
 
 [dev-dependencies]

diff --git a/hal/src/adc.rs b/hal/src/adc.rs
@@ -149,19 +149,19 @@ pub enum Clk {
 impl Clk {
     const fn ckmode(&self) -> pac::adc::cfgr2::CKMODE_A {
         match self {
-            Clk::RccHsi | Clk::RccPllP | Clk::RccSysClk => pac::adc::cfgr2::CKMODE_A::ADCLK,
-            Clk::PClkDiv2 => pac::adc::cfgr2::CKMODE_A::PCLK_DIV2,
-            Clk::PClkDiv4 => pac::adc::cfgr2::CKMODE_A::PCLK_DIV4,
-            Clk::PClk => pac::adc::cfgr2::CKMODE_A::PCLK,
+            Clk::RccHsi | Clk::RccPllP | Clk::RccSysClk => pac::adc::cfgr2::CKMODE_A::Adclk,
+            Clk::PClkDiv2 => pac::adc::cfgr2::CKMODE_A::PclkDiv2,
+            Clk::PClkDiv4 => pac::adc::cfgr2::CKMODE_A::PclkDiv4,
+            Clk::PClk => pac::adc::cfgr2::CKMODE_A::Pclk,
         }
     }
 
     const fn adcsel(&self) -> pac::rcc::ccipr::ADCSEL_A {
         match self {
-            Clk::RccHsi => pac::rcc::ccipr::ADCSEL_A::HSI16,
-            Clk::RccPllP => pac::rcc::ccipr::ADCSEL_A::PLLP,
-            Clk::RccSysClk => pac::rcc::ccipr::ADCSEL_A::SYSCLK,
-            _ => pac::rcc::ccipr::ADCSEL_A::NOCLOCK,
+            Clk::RccHsi => pac::rcc::ccipr::ADCSEL_A::Hsi16,
+            Clk::RccPllP => pac::rcc::ccipr::ADCSEL_A::Pllp,
+            Clk::RccSysClk => pac::rcc::ccipr::ADCSEL_A::Sysclk,
+            _ => pac::rcc::ccipr::ADCSEL_A::NoClock,
         }
     }
 }
@@ -579,15 +579,15 @@ impl Adc {
         use pac::{adc::cfgr2::CKMODE_A, rcc::ccipr::ADCSEL_A};
 
         match self.adc.cfgr2.read().ckmode().variant() {
-            CKMODE_A::ADCLK => match rcc.ccipr.read().adcsel().variant() {
-                ADCSEL_A::NOCLOCK => None,
-                ADCSEL_A::HSI16 => Some(Clk::RccHsi),
-                ADCSEL_A::PLLP => Some(Clk::RccPllP),
-                ADCSEL_A::SYSCLK => Some(Clk::RccSysClk),
+            CKMODE_A::Adclk => match rcc.ccipr.read().adcsel().variant() {
+                ADCSEL_A::NoClock => None,
+                ADCSEL_A::Hsi16 => Some(Clk::RccHsi),
+                ADCSEL_A::Pllp => Some(Clk::RccPllP),
+                ADCSEL_A::Sysclk => Some(Clk::RccSysClk),
             },
-            CKMODE_A::PCLK_DIV2 => Some(Clk::PClkDiv2),
-            CKMODE_A::PCLK_DIV4 => Some(Clk::PClkDiv4),
-            CKMODE_A::PCLK => Some(Clk::PClk),
+            CKMODE_A::PclkDiv2 => Some(Clk::PClkDiv2),
+            CKMODE_A::PclkDiv4 => Some(Clk::PClkDiv4),
+            CKMODE_A::Pclk => Some(Clk::PClk),
         }
     }
 
@@ -656,30 +656,30 @@ impl Adc {
         };
 
         let source_freq: Ratio<u32> = match self.adc.cfgr2.read().ckmode().variant() {
-            CKMODE_A::ADCLK => {
+            CKMODE_A::Adclk => {
                 let src: Ratio<u32> = match rcc.ccipr.read().adcsel().variant() {
-                    ADCSEL_A::NOCLOCK => Ratio::new_raw(0, 1),
-                    ADCSEL_A::HSI16 => Ratio::new_raw(16_000_000, 1),
-                    ADCSEL_A::PLLP => crate::rcc::pllpclk(rcc, &rcc.pllcfgr.read()),
-                    ADCSEL_A::SYSCLK => crate::rcc::sysclk(rcc, &rcc.cfgr.read()),
+                    ADCSEL_A::NoClock => Ratio::new_raw(0, 1),
+                    ADCSEL_A::Hsi16 => Ratio::new_raw(16_000_000, 1),
+                    ADCSEL_A::Pllp => crate::rcc::pllpclk(rcc, &rcc.pllcfgr.read()),
+                    ADCSEL_A::Sysclk => crate::rcc::sysclk(rcc, &rcc.cfgr.read()),
                 };
 
                 // only the asynchronous clocks have the prescaler applied
                 let ccr = self.adc.ccr.read();
                 let prescaler: u32 = match ccr.presc().variant() {
                     Some(p) => match p {
-                        PRESC_A::DIV1 => 1,
-                        PRESC_A::DIV2 => 2,
-                        PRESC_A::DIV4 => 4,
-                        PRESC_A::DIV6 => 6,
-                        PRESC_A::DIV8 => 8,
-                        PRESC_A::DIV10 => 10,
-                        PRESC_A::DIV12 => 12,
-                        PRESC_A::DIV16 => 16,
-                        PRESC_A::DIV32 => 32,
-                        PRESC_A::DIV64 => 64,
-                        PRESC_A::DIV128 => 128,
-                        PRESC_A::DIV256 => 256,
+                        PRESC_A::Div1 => 1,
+                        PRESC_A::Div2 => 2,
+                        PRESC_A::Div4 => 4,
+                        PRESC_A::Div6 => 6,
+                        PRESC_A::Div8 => 8,
+                        PRESC_A::Div10 => 10,
+                        PRESC_A::Div12 => 12,
+                        PRESC_A::Div16 => 16,
+                        PRESC_A::Div32 => 32,
+                        PRESC_A::Div64 => 64,
+                        PRESC_A::Div128 => 128,
+                        PRESC_A::Div256 => 256,
                     },
                     None => {
                         error!("Reserved ADC prescaler value {:#X}", ccr.presc().bits());
@@ -689,9 +689,9 @@ impl Adc {
 
                 src / prescaler
             }
-            CKMODE_A::PCLK_DIV2 => crate::rcc::pclk2(rcc, &rcc.cfgr.read()) / 2,
-            CKMODE_A::PCLK_DIV4 => crate::rcc::pclk2(rcc, &rcc.cfgr.read()) / 4,
-            CKMODE_A::PCLK => crate::rcc::pclk2(rcc, &rcc.cfgr.read()),
+            CKMODE_A::PclkDiv2 => crate::rcc::pclk2(rcc, &rcc.cfgr.read()) / 2,
+            CKMODE_A::PclkDiv4 => crate::rcc::pclk2(rcc, &rcc.cfgr.read()) / 4,
+            CKMODE_A::Pclk => crate::rcc::pclk2(rcc, &rcc.cfgr.read()),
         };
 
         source_freq.to_integer()

diff --git a/hal/src/aes.rs b/hal/src/aes.rs
@@ -167,7 +167,7 @@ impl Aes {
 
         Aes {
             aes,
-            swap_mode: SwapMode::NONE,
+            swap_mode: SwapMode::None,
         }
     }
 
@@ -275,7 +275,7 @@ impl Aes {
     pub const unsafe fn new_no_init(aes: pac::AES) -> Aes {
         Aes {
             aes,
-            swap_mode: SwapMode::NONE,
+            swap_mode: SwapMode::None,
         }
     }
 
@@ -316,7 +316,7 @@ impl Aes {
         let dp: pac::Peripherals = pac::Peripherals::steal();
         Aes {
             aes: dp.AES,
-            swap_mode: SwapMode::NONE,
+            swap_mode: SwapMode::None,
         }
     }
 
@@ -346,7 +346,7 @@ impl Aes {
                 self.aes.keyr2.write(|w| w.key().bits(key[1]));
                 self.aes.keyr1.write(|w| w.key().bits(key[2]));
                 self.aes.keyr0.write(|w| w.key().bits(key[3]));
-                KeySize::BITS128
+                KeySize::Bits128
             }
             8 => {
                 self.aes.cr.write(|w| w.en().disabled().keysize().bits256());
@@ -358,7 +358,7 @@ impl Aes {
                 self.aes.keyr2.write(|w| w.key().bits(key[5]));
                 self.aes.keyr1.write(|w| w.key().bits(key[6]));
                 self.aes.keyr0.write(|w| w.key().bits(key[7]));
-                KeySize::BITS256
+                KeySize::Bits256
             }
             _ => panic!("Key must be 128-bit or 256-bit not {}-bit", key.len() * 32),
         }
@@ -793,7 +793,7 @@ impl Aes {
     ///
     /// let mut dp: pac::Peripherals = pac::Peripherals::take().unwrap();
     /// let mut aes: Aes = Aes::new(dp.AES, &mut dp.RCC);
-    /// let mut rng = Rng::new(dp.RNG, rng::Clk::MSI, &mut dp.RCC);
+    /// let mut rng = Rng::new(dp.RNG, rng::Clk::Msi, &mut dp.RCC);
     ///
     /// const KEY: [u32; 4] = [0; 4];
     ///
@@ -840,7 +840,7 @@ impl Aes {
     ///
     /// let mut dp: pac::Peripherals = pac::Peripherals::take().unwrap();
     /// let mut aes: Aes = Aes::new(dp.AES, &mut dp.RCC);
-    /// let mut rng = Rng::new(dp.RNG, rng::Clk::MSI, &mut dp.RCC);
+    /// let mut rng = Rng::new(dp.RNG, rng::Clk::Msi, &mut dp.RCC);
     ///
     /// const KEY: [u32; 4] = [0; 4];
     ///

diff --git a/hal/src/dac.rs b/hal/src/dac.rs
@@ -32,12 +32,12 @@ pub enum ModePin {
 impl From<ModePin> for MODE1_A {
     fn from(mp: ModePin) -> Self {
         match mp {
-            ModePin::NormBuf => MODE1_A::NORMALPINBUFFER,
-            ModePin::NormChipBuf => MODE1_A::NORMALPINCHIPBUFFER,
-            ModePin::NormNoBuf => MODE1_A::NORMALPINNOBUFFER,
-            ModePin::SampleHoldBuf => MODE1_A::SHPINBUFFER,
-            ModePin::SampleHoldChipBuf => MODE1_A::SHPINCHIPBUFFER,
-            ModePin::SampleHoldNoBuf => MODE1_A::SHPINNOBUFFER,
+            ModePin::NormBuf => MODE1_A::NormalPinBuffer,
+            ModePin::NormChipBuf => MODE1_A::NormalPinChipBuffer,
+            ModePin::NormNoBuf => MODE1_A::NormalPinNoBuffer,
+            ModePin::SampleHoldBuf => MODE1_A::ShpinBuffer,
+            ModePin::SampleHoldChipBuf => MODE1_A::ShpinChipBuffer,
+            ModePin::SampleHoldNoBuf => MODE1_A::ShpinNoBuffer,
         }
     }
 }
@@ -60,8 +60,8 @@ pub enum ModeChip {
 impl From<ModeChip> for MODE1_A {
     fn from(mc: ModeChip) -> Self {
         match mc {
-            ModeChip::SampleHold => MODE1_A::SHCHIPNOBUFFER,
-            ModeChip::Norm => MODE1_A::NORMALCHIPNOBUFFER,
+            ModeChip::SampleHold => MODE1_A::ShchipNoBuffer,
+            ModeChip::Norm => MODE1_A::NormalChipNoBuffer,
         }
     }
 }

diff --git a/hal/src/i2c.rs b/hal/src/i2c.rs
@@ -346,9 +346,9 @@ macro_rules! impl_clocks_reset {
                 fn clock(rcc: &RCC) -> u32 {
                     // NOTE(unsafe) atomic read with no side effects
                     match rcc.ccipr.read().$i2cXsel().variant().unwrap() {
-                        I2C3SEL_A::HSI16 => 16_000_000,
-                        I2C3SEL_A::SYSCLK => sysclk_hz(rcc),
-                        I2C3SEL_A::PCLK => pclk1_hz(rcc),
+                        I2C3SEL_A::Hsi16 => 16_000_000,
+                        I2C3SEL_A::Sysclk => sysclk_hz(rcc),
+                        I2C3SEL_A::Pclk => pclk1_hz(rcc),
                     }
                 }
             }

diff --git a/hal/src/pka.rs b/hal/src/pka.rs
@@ -505,7 +505,7 @@ impl Pka {
             self.clear_all_flags();
             Err(EcdsaSignError::Ram)
         } else {
-            self.start_process(MODE_A::ECDSASIGN);
+            self.start_process(MODE_A::Ecdsasign);
             Ok(())
         }
     }
@@ -639,7 +639,7 @@ impl Pka {
             self.clear_all_flags();
             Err(EcdsaVerifyError::Ram)
         } else {
-            self.start_process(MODE_A::ECDSAVERIF);
+            self.start_process(MODE_A::Ecdsaverif);
             Ok(())
         }
     }