Set harness clock to default clk freq | Use combined clk frag.

[abejgonzalez]

Use the nicer WithUniformBusFrequencies fragment which sets all the buses to the same clock. Additionally set the harness clock to the same frequency (otherwise the harness clock is set to 100MHz by default).

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[jerryz123]

What is this change for? I believe leaving the harness at 100 MHz keeps it more "test-chip-like", since the FPGA-side "harness" won't run at more than 100 MHz.

[abejgonzalez]

What is this change for? I believe leaving the harness at 100 MHz keeps it more "test-chip-like", since the FPGA-side "harness" won't run at more than 100 MHz.

This was to generate a single clock for the entire system s.t. waveforms see 1 uniform clock (I assume VCS/Verilator properly remove dead cycles if the harness/chiptop have different frequencies). This is more cosmetic than anything, I'll close.