Skip to content

aarch64: add exception syndrome (ESR) pseudo-register #841

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
wants to merge 1 commit into
base: master
Choose a base branch
from
Open

aarch64: add exception syndrome (ESR) pseudo-register #841

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
9 changes: 5 additions & 4 deletions bindings/dotnet/UnicornManaged/Const/Arm64.fs
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -273,12 +273,13 @@ module Arm64 =
// pseudo registers
let UC_ARM64_REG_PC = 260
let UC_ARM64_REG_CPACR_EL1 = 261
let UC_ARM64_REG_ESR = 262

// thread registers
let UC_ARM64_REG_TPIDR_EL0 = 262
let UC_ARM64_REG_TPIDRRO_EL0 = 263
let UC_ARM64_REG_TPIDR_EL1 = 264
let UC_ARM64_REG_ENDING = 265
let UC_ARM64_REG_TPIDR_EL0 = 263
let UC_ARM64_REG_TPIDRRO_EL0 = 264
let UC_ARM64_REG_TPIDR_EL1 = 265
let UC_ARM64_REG_ENDING = 266

// alias registers
let UC_ARM64_REG_IP1 = 215
Expand Down
9 changes: 5 additions & 4 deletions bindings/go/unicorn/arm64_const.go
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -268,12 +268,13 @@ const (
// pseudo registers
ARM64_REG_PC = 260
ARM64_REG_CPACR_EL1 = 261
ARM64_REG_ESR = 262

// thread registers
ARM64_REG_TPIDR_EL0 = 262
ARM64_REG_TPIDRRO_EL0 = 263
ARM64_REG_TPIDR_EL1 = 264
ARM64_REG_ENDING = 265
ARM64_REG_TPIDR_EL0 = 263
ARM64_REG_TPIDRRO_EL0 = 264
ARM64_REG_TPIDR_EL1 = 265
ARM64_REG_ENDING = 266

// alias registers
ARM64_REG_IP1 = 215
Expand Down
9 changes: 5 additions & 4 deletions bindings/java/unicorn/Arm64Const.java
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -270,12 +270,13 @@ public interface Arm64Const {
// pseudo registers
public static final int UC_ARM64_REG_PC = 260;
public static final int UC_ARM64_REG_CPACR_EL1 = 261;
public static final int UC_ARM64_REG_ESR = 262;

// thread registers
public static final int UC_ARM64_REG_TPIDR_EL0 = 262;
public static final int UC_ARM64_REG_TPIDRRO_EL0 = 263;
public static final int UC_ARM64_REG_TPIDR_EL1 = 264;
public static final int UC_ARM64_REG_ENDING = 265;
public static final int UC_ARM64_REG_TPIDR_EL0 = 263;
public static final int UC_ARM64_REG_TPIDRRO_EL0 = 264;
public static final int UC_ARM64_REG_TPIDR_EL1 = 265;
public static final int UC_ARM64_REG_ENDING = 266;

// alias registers
public static final int UC_ARM64_REG_IP1 = 215;
Expand Down
9 changes: 5 additions & 4 deletions bindings/python/unicorn/arm64_const.py
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -266,12 +266,13 @@
# pseudo registers
UC_ARM64_REG_PC = 260
UC_ARM64_REG_CPACR_EL1 = 261
UC_ARM64_REG_ESR = 262

# thread registers
UC_ARM64_REG_TPIDR_EL0 = 262
UC_ARM64_REG_TPIDRRO_EL0 = 263
UC_ARM64_REG_TPIDR_EL1 = 264
UC_ARM64_REG_ENDING = 265
UC_ARM64_REG_TPIDR_EL0 = 263
UC_ARM64_REG_TPIDRRO_EL0 = 264
UC_ARM64_REG_TPIDR_EL1 = 265
UC_ARM64_REG_ENDING = 266

# alias registers
UC_ARM64_REG_IP1 = 215
Expand Down
9 changes: 5 additions & 4 deletions bindings/ruby/unicorn_gem/lib/unicorn/arm64_const.rb
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -268,12 +268,13 @@ module Unicorn
# pseudo registers
UC_ARM64_REG_PC = 260
UC_ARM64_REG_CPACR_EL1 = 261
UC_ARM64_REG_ESR = 262

# thread registers
UC_ARM64_REG_TPIDR_EL0 = 262
UC_ARM64_REG_TPIDRRO_EL0 = 263
UC_ARM64_REG_TPIDR_EL1 = 264
UC_ARM64_REG_ENDING = 265
UC_ARM64_REG_TPIDR_EL0 = 263
UC_ARM64_REG_TPIDRRO_EL0 = 264
UC_ARM64_REG_TPIDR_EL1 = 265
UC_ARM64_REG_ENDING = 266

# alias registers
UC_ARM64_REG_IP1 = 215
Expand Down
2 changes: 2 additions & 0 deletions include/unicorn/arm64.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -282,6 +282,8 @@ typedef enum uc_arm64_reg {

UC_ARM64_REG_CPACR_EL1,

UC_ARM64_REG_ESR, // exception syndrome register

//> thread registers
UC_ARM64_REG_TPIDR_EL0,
UC_ARM64_REG_TPIDRRO_EL0,
Expand Down
3 changes: 3 additions & 0 deletions qemu/target-arm/unicorn_aarch64.c
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -79,6 +79,9 @@ int arm64_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int co
case UC_ARM64_REG_CPACR_EL1:
*(uint32_t *)value = ARM_CPU(uc, mycpu)->env.cp15.c1_coproc;
break;
case UC_ARM64_REG_ESR:
*(uint32_t *)value = ARM_CPU(uc, mycpu)->env.exception.syndrome;
break;
case UC_ARM64_REG_TPIDR_EL0:
*(int64_t *)value = ARM_CPU(uc, mycpu)->env.cp15.tpidr_el0;
break;
Expand Down