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1. ysyx-workbench ysyx-workbench Public

   一生一芯CPU/目前做到cache/后续主要考虑ASIC DV

   C 19 1

2. Eth_Switch_IP Eth_Switch_IP Public

   第八届集创赛中科芯杯

   Verilog 5

3. Pango-FPGA Pango-FPGA Public

   第七届全国大学生嵌入式芯片与系统设计竞赛FPGA创新设计赛道——紫光同创杯

   Verilog 3

4. MIT-course-training MIT-course-training Public

   MIT6.004/MIT6.175/MIT6.375

   C 2

5. rtl_design_for_interview rtl_design_for_interview Public

   A repository to store basic rtl designs for interview.

   SystemVerilog

6. axi_crossbar_dv axi_crossbar_dv Public

   SystemVerilog