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boards: mps4: Enable non-secure variant support #95105

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f6493e8
boards: mps4: Enable non-secure variant support
wearyzen Jun 11, 2025
5e7bd25
boards: arm: fix generation of DDR4 memory section
wearyzen Jul 23, 2025
9e516ee
doc: update TF-M requirements
wearyzen Aug 28, 2025
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11 changes: 10 additions & 1 deletion boards/arm/mps4/board.cmake
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Original file line number Diff line number Diff line change
Expand Up @@ -27,7 +27,16 @@ if(CONFIG_BOARD_MPS4_CORSTONE315_FVP OR CONFIG_BOARD_MPS4_CORSTONE320_FVP)
endif()

if(CONFIG_BUILD_WITH_TFM)
set(ARMFVP_FLAGS ${ARMFVP_FLAGS} -a ${APPLICATION_BINARY_DIR}/zephyr/tfm_merged.hex)
# Workaround: Use binary (.bin) format images until TF-M supports generating them in hex (.hex)
# format. The image load addresses are referred from the TF-M official documentation at:
# https://trustedfirmware-m.readthedocs.io/en/latest/platform/arm/mps4/corstone320/README.html
set(ARMFVP_FLAGS ${ARMFVP_FLAGS}
--data ${APPLICATION_BINARY_DIR}/tfm/bin/bl1_1.bin@0x11000000
--data ${APPLICATION_BINARY_DIR}/tfm/bin/cm_provisioning_bundle.bin@0x12024000
--data ${APPLICATION_BINARY_DIR}/tfm/bin/dm_provisioning_bundle.bin@0x1202aa00
--data ${APPLICATION_BINARY_DIR}/tfm/bin/bl2_signed.bin@0x12031400
-a ${APPLICATION_BINARY_DIR}/zephyr/tfm_merged.hex
)
endif()

# FVP Parameters
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15 changes: 0 additions & 15 deletions boards/arm/mps4/mps4_common.dtsi
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Expand Up @@ -97,21 +97,6 @@
zephyr,memory-region = "NULL_PTR_DETECT";
zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_FLASH) )>;
};

/* DDR4 - 2G, alternates non-secure/secure every 256M */
ddr4: memory@60000000 {
device_type = "memory";
compatible = "zephyr,memory-region";
reg = <0x60000000 DT_SIZE_M(256)
0x70000000 DT_SIZE_M(256)
0x80000000 DT_SIZE_M(256)
0x90000000 DT_SIZE_M(256)
0xa0000000 DT_SIZE_M(256)
0xb0000000 DT_SIZE_M(256)
0xc0000000 DT_SIZE_M(256)
0xd0000000 DT_SIZE_M(256)>;
zephyr,memory-region = "DDR4";
};
};

&nvic {
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53 changes: 53 additions & 0 deletions boards/arm/mps4/mps4_corstone315_fvp.dts
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Expand Up @@ -83,6 +83,59 @@
zephyr,memory-region = "ISRAM";
};

/* The DDR4 node and zephyr,memory-region follow the naming convention
* ddr4_$IDAUID_$SECURITY_FLAG except for the default region of board
* which is named as "DDR4" to be compatible with existing
* samples/tests that expect DDR4 node and region to be of the same name.
*/
ddr4_6_ns: memory@60000000 {
compatible = "zephyr,memory-region";
reg = <0x60000000 DT_SIZE_M(256)>;
zephyr,memory-region = "DDR4_6_NS";
};

ddr4: memory@70000000 {
compatible = "zephyr,memory-region";
reg = <0x70000000 DT_SIZE_M(256)>;
zephyr,memory-region = "DDR4";
};

ddr4_8_ns: memory@80000000 {
compatible = "zephyr,memory-region";
reg = <0x80000000 DT_SIZE_M(256)>;
zephyr,memory-region = "DDR4_8_NS";
};

ddr4_9_s: memory@90000000 {
compatible = "zephyr,memory-region";
reg = <0x90000000 DT_SIZE_M(256)>;
zephyr,memory-region = "DDR4_9_S";
};

ddr4_a_ns: memory@a0000000 {
compatible = "zephyr,memory-region";
reg = <0xa0000000 DT_SIZE_M(256)>;
zephyr,memory-region = "DDR4_A_NS";
};

ddr4_b_s: memory@b0000000 {
compatible = "zephyr,memory-region";
reg = <0xb0000000 DT_SIZE_M(256)>;
zephyr,memory-region = "DDR4_B_S";
};

ddr4_c_ns: memory@c0000000 {
compatible = "zephyr,memory-region";
reg = <0xc0000000 DT_SIZE_M(256)>;
zephyr,memory-region = "DDR4_C_NS";
};

ddr4_d_s: memory@d0000000 {
compatible = "zephyr,memory-region";
reg = <0xd0000000 DT_SIZE_M(256)>;
zephyr,memory-region = "DDR4_D_S";
};

soc {
peripheral@50000000 {
#address-cells = <1>;
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29 changes: 29 additions & 0 deletions boards/arm/mps4/mps4_corstone315_fvp_ns.dts
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Original file line number Diff line number Diff line change
Expand Up @@ -68,6 +68,35 @@
zephyr,memory-region = "ISRAM";
};

/* The DDR4 node and zephyr,memory-region follow the naming convention
* ddr4_$IDAUID_$SECURITY_FLAG except for the default region of board
* which is named as "DDR4" to be compatible with existing
* samples/tests that expect DDR4 node and region to be of the same name.
*/
ddr4: memory@60000000 {
compatible = "zephyr,memory-region";
reg = <0x60000000 DT_SIZE_M(256)>;
zephyr,memory-region = "DDR4";
};

ddr4_8_ns: memory@80000000 {
compatible = "zephyr,memory-region";
reg = <0x80000000 DT_SIZE_M(256)>;
zephyr,memory-region = "DDR4_8_NS";
};

ddr4_a_ns: memory@a0000000 {
compatible = "zephyr,memory-region";
reg = <0xa0000000 DT_SIZE_M(256)>;
zephyr,memory-region = "DDR4_A_NS";
};

ddr4_c_ns: memory@c0000000 {
compatible = "zephyr,memory-region";
reg = <0xc0000000 DT_SIZE_M(256)>;
zephyr,memory-region = "DDR4_C_NS";
};

reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
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15 changes: 0 additions & 15 deletions boards/arm/mps4/mps4_corstone315_fvp_ns.yaml
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53 changes: 53 additions & 0 deletions boards/arm/mps4/mps4_corstone320_fvp.dts
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Original file line number Diff line number Diff line change
Expand Up @@ -83,6 +83,59 @@
zephyr,memory-region = "ISRAM";
};

/* The DDR4 node and zephyr,memory-region follow the naming convention
* ddr4_$IDAUID_$SECURITY_FLAG except for the default region of board
* which is named as "DDR4" to be compatible with existing
* samples/tests that expect DDR4 node and region to be of the same name.
*/
ddr4_6_ns: memory@60000000 {
compatible = "zephyr,memory-region";
reg = <0x60000000 DT_SIZE_M(256)>;
zephyr,memory-region = "DDR4_6_NS";
};

ddr4: memory@70000000 {
compatible = "zephyr,memory-region";
reg = <0x70000000 DT_SIZE_M(256)>;
zephyr,memory-region = "DDR4";
};

ddr4_8_ns: memory@80000000 {
compatible = "zephyr,memory-region";
reg = <0x80000000 DT_SIZE_M(256)>;
zephyr,memory-region = "DDR4_8_NS";
};

ddr4_9_s: memory@90000000 {
compatible = "zephyr,memory-region";
reg = <0x90000000 DT_SIZE_M(256)>;
zephyr,memory-region = "DDR4_9_S";
};

ddr4_a_ns: memory@a0000000 {
compatible = "zephyr,memory-region";
reg = <0xa0000000 DT_SIZE_M(256)>;
zephyr,memory-region = "DDR4_A_NS";
};

ddr4_b_s: memory@b0000000 {
compatible = "zephyr,memory-region";
reg = <0xb0000000 DT_SIZE_M(256)>;
zephyr,memory-region = "DDR4_B_S";
};

ddr4_c_ns: memory@c0000000 {
compatible = "zephyr,memory-region";
reg = <0xc0000000 DT_SIZE_M(256)>;
zephyr,memory-region = "DDR4_C_NS";
};

ddr4_d_s: memory@d0000000 {
compatible = "zephyr,memory-region";
reg = <0xd0000000 DT_SIZE_M(256)>;
zephyr,memory-region = "DDR4_D_S";
};

soc {
peripheral@50000000 {
#address-cells = <1>;
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29 changes: 29 additions & 0 deletions boards/arm/mps4/mps4_corstone320_fvp_ns.dts
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Original file line number Diff line number Diff line change
Expand Up @@ -68,6 +68,35 @@
zephyr,memory-region = "ISRAM";
};

/* The DDR4 node and zephyr,memory-region follow the naming convention
* ddr4_$IDAUID_$SECURITY_FLAG except for the default region of board
* which is named as "DDR4" to be compatible with existing
* samples/tests that expect DDR4 node and region to be of the same name.
*/
ddr4: memory@60000000 {
compatible = "zephyr,memory-region";
reg = <0x60000000 DT_SIZE_M(256)>;
zephyr,memory-region = "DDR4";
};

ddr4_8_ns: memory@80000000 {
compatible = "zephyr,memory-region";
reg = <0x80000000 DT_SIZE_M(256)>;
zephyr,memory-region = "DDR4_8_NS";
};

ddr4_a_ns: memory@a0000000 {
compatible = "zephyr,memory-region";
reg = <0xa0000000 DT_SIZE_M(256)>;
zephyr,memory-region = "DDR4_A_NS";
};

ddr4_c_ns: memory@c0000000 {
compatible = "zephyr,memory-region";
reg = <0xc0000000 DT_SIZE_M(256)>;
zephyr,memory-region = "DDR4_C_NS";
};

reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
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15 changes: 0 additions & 15 deletions boards/arm/mps4/mps4_corstone320_fvp_ns.yaml
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22 changes: 11 additions & 11 deletions doc/services/tfm/requirements.rst
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Expand Up @@ -11,7 +11,13 @@ The following are some of the boards that can be used with TF-M:
* - :ref:`mps2_an521_board`
- ``mps2/an521/cpu0/ns`` (qemu supported)
* - :ref:`mps3_board`
- ``mps3/corstone300/an547/ns`` (qemu supported)
-
- ``mps3/corstone300/fvp/ns`` (armfvp supported)
- ``mps3/corstone310/fvp/ns`` (armfvp supported)
* - :zephyr:board:`mps4`
-
- ``mps4/corstone315/fvp/ns`` (armfvp supported)
- ``mps4/corstone320/fvp/ns`` (armfvp supported)
* - :zephyr:board:`bl5340_dvk`
- ``bl5340_dvk/nrf5340/cpuapp/ns``
* - :zephyr:board:`lpcxpresso55s69`
Expand All @@ -38,21 +44,15 @@ is set to ``y`` in that board's default configuration.
Software Requirements
*********************

The following Python modules are required when building TF-M binaries:

* cryptography
* pyasn1
* pyyaml
* cbor>=1.0.0
* imgtool>=1.9.0
* jinja2
* click
The Python modules required when building TF-M binaries are listed in the
TF-M repository under ``tools/requirements.txt``. Because module locations
can vary across workspaces, use ``west`` to locate TF-M before installing.

You can install them via:

.. code-block:: bash

$ pip3 install --user cryptography pyasn1 pyyaml cbor>=1.0.0 imgtool>=1.9.0 jinja2 click
$ pip3 install -r "$(west list trusted-firmware-m -f '{abspath}')/tools/requirements.txt"

They are used by TF-M's signing utility to prepare firmware images for
validation by the bootloader.
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2 changes: 2 additions & 0 deletions modules/trusted-firmware-m/Kconfig.tfm
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Expand Up @@ -17,6 +17,8 @@ config TFM_BOARD
default "arm/mps3/corstone300/an552" if BOARD_MPS3_CORSTONE300_AN552_NS
default "arm/mps3/corstone310/an555" if BOARD_MPS3_CORSTONE310_AN555_NS
default "arm/mps3/corstone310/fvp" if BOARD_MPS3_CORSTONE310_FVP_NS
default "arm/mps4/corstone315" if BOARD_MPS4_CORSTONE315_FVP_NS
default "arm/mps4/corstone320" if BOARD_MPS4_CORSTONE320_FVP_NS
default "stm/b_u585i_iot02a" if BOARD_B_U585I_IOT02A
default "stm/nucleo_l552ze_q" if BOARD_NUCLEO_L552ZE_Q
default "stm/stm32l562e_dk" if BOARD_STM32L562E_DK
Expand Down