initial commit.

.gitignore

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+build*/
+bstreams/
+iprepo/
+tmp/
+hd_visual/
+ip_dir/
+xsim.dir/
+tb_user/
+ip/
+.Xil/
+.vscode/
+*.pb
+*.log
+*.tmp
+*.jou
+*.str
+*.xml
+*.config
+*.zip
+

.gitmodules

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+[submodule "hw/ext/network"]
+	path = hw/ext/network
+	url = https://github.com/fpgasystems/fpga-network-stack.git
+	branch = master

README.md

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+# Coyote
+Reconfigurable Heterogeneous Architecture Framework aiming to provide operating system abstractions.
+
+## Prerequisites
+Framework was tested with `Vivado 2019.2` and `Vivado 2020.1`. Following Xilinx platforms are supported: `vcu118`, `Alveo u250`, `Alveo u280`. Minimum version of CMake required is 3.0.
+
+## Dependencies
+Initiate the network stack:
+
+	$ git clone
+	$ git submodule update --init --recursive
+
+## Build `HW`
+
+Create a build directory:
+
+	$ cd hw
+	$ mkdir build
+	$ cd build
+
+Enter a valid system configuration:
+
+	$ cmake .. -DFDEV_NAME=u250 <params...>
+
+Following configuration options are provided:
+
+| Name                   | Values                   | Desription                                                                         |
+|------------------------|--------------------------|------------------------------------------------------------------------------------|
+| FDEV\_NAME             | <**u250**, u280, vcu118> | Supported devices                                                                  |
+| N\_REGIONS             | <**1**:16>               | Number of independent regions                                                      |
+| EN\_STRM               | <0, **1**>               | Enable direct host-fpga streaming                                                  |
+| EN\_DDR                | <**0**, 1>               | Enable local FPGA memory stack                                                     |
+| EN\_AVX                | <0,**1**>                | AVX support                                                                        |
+| EN\_BPSS               | <0,**1**>                | Bypass descriptors in user logic                                                   |
+| N\_DDR\_CHAN           | <0:4>                    | Number of DDR channels in striping mode                                            |
+| EN\_PR                 | <**0**, 1>               | Enable dynamic reconfiguration of the regions                                      |
+| EN\_TCP                | <**0**, 1>               | Enable TCP/IP stack                                                          		 |
+| EN\_RDMA               | <**0**, 1>               | Enable RDMA stack   															     |
+| EN\_FVV                | <**0**, 1>               | Enable Farview verbs                                                               |
+
+If network stack is used, the IP dependencies can be installed with:
+
+	make installip
+
+Create the shell and the project:
+
+	make shell
+
+If PR is enabled, additional sets of configurations can be added by running the following command:
+
+	make dynamic
+
+At this point user logic can be inserted. User logic wrappers can be found under build project directory in the **hdl/config_X** where **X** represents the chosen PR configuration. If multiple PR configurations are present it is advisable to put the most complex configuration in the initial one (**config_0**). For best results explicit floorplanning should be done manually after synthesis. 
+
+Once the user design is ready to be compiled, run the following command:
+
+	make compile
+
+Once the compilation finishes, the initial bitstream with the static region can be loaded to the FPGA via JTAG. At any point during the compilation, the status can be checked by opening the project in Vivado. This can be done by running `start_gui` in the same terminal shell. All compiled bitstreams, including partial ones, can be found in the build directory under **bitstreams**.
+
+## Driver
+
+After the bitstream has been loaded, the driver can be compiled on the target host machine:
+
+	cd driver
+	make
+
+Insert the driver into the kernel:
+
+	insmod fpga_drv.ko 
+
+Run the script **util/hot_reset.sh** to rescan the PCIe. If this fails the restart of the machine might be necessary after this step.
+
+## Build `SW`
+
+Any of the `sw` projects can be built with the following commands:
+
+	cd sw/<project>
+	mkdir build
+	cd build
+	cmake ..
+	make main
+
+## Simulation
+
+User logic can be simulated by creating the testbench project:
+
+	cd hw/sim/scripts/sim
+	vivado -mode tcl -source tb.tcl

cmake/FindVivado.cmake

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+# Author:  Johannes de Fine Licht ([email protected])
+# Created: October 2016
+#
+# To specify the path to the Vivado installation, provide:
+#   -DVIVADO_ROOT_DIR=<installation directory>
+# If successful, this script defines:
+#   VIVADO_FOUND
+#   VIVADO_BINARY
+
+cmake_minimum_required(VERSION 3.0)
+
+find_path(VIVADO_PATH
+  NAMES vivado 
+  PATHS ${VIVADO_ROOT_DIR} ENV XILINX_VIVADO
+  PATH_SUFFIXES bin
+)
+
+if(NOT EXISTS ${VIVADO_PATH})
+
+  message(WARNING "Vivado not found.")
+
+else()
+
+  get_filename_component(VIVADO_ROOT_DIR ${VIVADO_PATH} DIRECTORY)
+
+  set(VIVADO_FOUND TRUE)
+  set(VIVADO_BINARY ${VIVADO_ROOT_DIR}/bin/vivado)
+
+  message(STATUS "Found Vivado at ${VIVADO_ROOT_DIR}.")
+
+endif()

cmake/FindVivadoHLS.cmake

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+# Author:  Johannes de Fine Licht ([email protected])
+# Created: October 2016
+#
+# To specify the path to the Vivado HLS installation, provide:
+#   -DVIVADO_HLS_ROOT_DIR=<installation directory>
+# If successful, this script defines:
+#   VIVADO_HLS_FOUND
+#   VIVADO_HLS_BINARY
+#   VIVADO_HLS_INCLUDE_DIRS
+
+cmake_minimum_required(VERSION 3.0)
+
+find_path(VIVADO_HLS_PATH
+  NAMES vivado_hls 
+  PATHS ${VIVADO_HLS_ROOT_DIR} ENV XILINX_VIVADO_HLS ENV XILINX_HLS
+  PATH_SUFFIXES bin
+)
+
+if(NOT EXISTS ${VIVADO_HLS_PATH})
+
+  message(WARNING "Vivado HLS not found.")
+
+else()
+
+  get_filename_component(VIVADO_HLS_ROOT_DIR ${VIVADO_HLS_PATH} DIRECTORY)
+
+  set(VIVADO_HLS_FOUND TRUE)
+  set(VIVADO_HLS_INCLUDE_DIRS ${VIVADO_HLS_ROOT_DIR}/include/)
+  set(VIVADO_HLS_BINARY ${VIVADO_HLS_ROOT_DIR}/bin/vivado_hls)
+
+  message(STATUS "Found Vivado HLS at ${VIVADO_HLS_ROOT_DIR}.")
+
+endif()

driver/Makefile

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+obj-m := fpga_drv.o
+
+KERNELDIR ?= /lib/modules/$(shell uname -r)/build
+PWD := $(shell pwd)
+
+ROOT := $(dir $(M))
+XILINXINCLUDE := -I$(ROOT)../include -I$(ROOT)/include
+
+all:
+	$(MAKE) -C $(KERNELDIR) M=$(PWD) modules
+
+clean:
+	rm -rf *.o *~ core .depend .*.cmd *.ko *.mod.c .tmp_versions *.order *.symvers