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240 Open 746 Closed
240 Open 746 Closed
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Issues list

[BUG REPORT] Rocket is traping to machine mode, even with no pending interrupt
#3732 opened Mar 21, 2025 by bantierr
[Bug Report] Directly using the status.SUM flag without verifying its validity (The validity of the SUM flag is influenced by the satp.MODE).
#3730 opened Mar 20, 2025 by heyfenny
Simulation times out when executing WFI with questa simulator
#3729 opened Mar 17, 2025 by nadasherif15
[BUG REPORT] Divider Module Performance Bug: EarlyOut Fails to Skip Iterations When Divisor Exceeds Dividend
#3727 opened Mar 14, 2025 by Heresyrac
Async register not needed in IntSyncCrossingSource?
#3726 opened Mar 12, 2025 by Kevin99214
Adding prefetchers causes rocket core to hang in firmware
#3720 opened Feb 27, 2025 by ColeStrickler
[Feature request] RISC-V CMO support
#3719 opened Feb 20, 2025 by caizixian
AXIToTL component can‘t support axi outstanding？
#3715 opened Feb 7, 2025 by AD738560581
Rational Crossing Reset Bug
#3713 opened Jan 31, 2025 by moniriki
1
Performance of rocket-chip
#3709 opened Jan 29, 2025 by cassebas
make verilog error
#3703 opened Dec 22, 2024 by abendezu10
4
Error 1 build-setup.sh: Build script failed with exit code 2 at step 5: Pre-compiling Chipyard Scala sources
#3701 opened Dec 10, 2024 by sking-007
Differences in performance of the lhu command on Rocket and spike
#3698 opened Nov 13, 2024 by 90ICEDA
1
Spike and rocket's csr registers behave differently
#3697 opened Nov 12, 2024 by 90ICEDA
RoCC Core Clock Gating Bug
#3695 opened Nov 8, 2024 by moniriki
3
A moderately dangerous interupt domain crossing bug
#3687 opened Sep 22, 2024 by DecodeTheEncoded
2
Cannot find *behav_srams.v` in generated verilog files
#3686 opened Sep 21, 2024 by xlgforever
CanAttachTile.crossingParams is inappropriately used.
#3685 opened Sep 16, 2024 by DecodeTheEncoded
4
Remove "master/slave" terminology from Rocket Chip repo
#3684 opened Sep 9, 2024 by ben-k
@lordspacehog
1
AMO inst based on a mmio address will cause a store/amo access fault
#3679 opened Aug 23, 2024 by csgxiong
Chisel generates invalid nesting of always blocks and/or initializations.
#3677 opened Aug 21, 2024 by leviathanch
2
Issue in VTestDriver__Trace__2__Slow.cpp
#3672 opened Aug 18, 2024 by gituserdeepika
Colliding module name: ALU
#3671 opened Aug 17, 2024 by leviathanch
3
Make verilog Error
#3657 opened Jul 24, 2024 by Krishnakumarmohanraj
4
unable to build the C emulator due to missing verilog.h file
#3656 opened Jul 3, 2024 by nhuynh368
2
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