add lane data width

.github/designs/blastoise/t1emu.json

@@ -9,7 +9,7 @@
   "asm.mmm": 50719,
   "asm.smoke": 8153,
   "intrinsic.conv2d_less_m2": 2825,
-  "intrinsic.linear_normalization": 3529,
+  "intrinsic.linear_normalization": 3530,
   "intrinsic.softmax": 7162,
   "rvv_bench.ascii_to_utf16": 11872,
   "rvv_bench.ascii_to_utf32": 4910,

.github/designs/blastoise/t1rocketemu.json

@@ -302,14 +302,14 @@
   "codegen.vor_vi": 196438,
   "codegen.vor_vv": 127579,
   "codegen.vor_vx": 272297,
-  "codegen.vredand_vs": 127647,
-  "codegen.vredmax_vs": 127647,
-  "codegen.vredmaxu_vs": 127647,
-  "codegen.vredmin_vs": 127647,
-  "codegen.vredminu_vs": 127647,
-  "codegen.vredor_vs": 127647,
-  "codegen.vredsum_vs": 127647,
-  "codegen.vredxor_vs": 127647,
+  "codegen.vredand_vs": 127458,
+  "codegen.vredmax_vs": 127458,
+  "codegen.vredmaxu_vs": 127458,
+  "codegen.vredmin_vs": 127458,
+  "codegen.vredminu_vs": 127458,
+  "codegen.vredor_vs": 127458,
+  "codegen.vredsum_vs": 127458,
+  "codegen.vredxor_vs": 127458,
   "codegen.vrem_vv": 148997,
   "codegen.vrem_vx": 680321,
   "codegen.vremu_vv": 149296,
@@ -484,8 +484,8 @@
   "codegen.vwmulsu_vx": 234685,
   "codegen.vwmulu_vv": 69024,
   "codegen.vwmulu_vx": 234685,
-  "codegen.vwredsum_vs": 70483,
-  "codegen.vwredsumu_vs": 70483,
+  "codegen.vwredsum_vs": 70326,
+  "codegen.vwredsumu_vs": 70326,
   "codegen.vwsub_vv": 67641,
   "codegen.vwsub_vx": 170131,
   "codegen.vwsub_wv": 74368,
@@ -500,9 +500,9 @@
   "codegen.vzext_vf2": 35727,
   "codegen.vzext_vf4": 9179,
   "intrinsic.conv2d_less_m2": 4359,
-  "intrinsic.linear_normalization": 4818,
+  "intrinsic.linear_normalization": 4819,
   "intrinsic.matmul": 156950,
-  "intrinsic.softmax": 9003,
+  "intrinsic.softmax": 7949,
   "mlir.axpy_masked": 11636,
   "mlir.conv": 298996,
   "mlir.hello": 371,
@@ -518,7 +518,7 @@
   "rvv_bench.ascii_to_utf32": 440566,
   "rvv_bench.byteswap": 449395,
   "rvv_bench.chacha20": 45624,
-  "rvv_bench.mandelbrot": 563959,
+  "rvv_bench.mandelbrot": 459794,
   "rvv_bench.memcpy": 1267552,
   "rvv_bench.memset": 510029,
   "rvv_bench.mergelines": 777753,

.github/designs/rookidee/t1rocketemu.json

@@ -233,14 +233,14 @@
   "codegen.vor_vi": 172977,
   "codegen.vor_vv": 77468,
   "codegen.vor_vx": 214202,
-  "codegen.vredand_vs": 77857,
-  "codegen.vredmax_vs": 77857,
-  "codegen.vredmaxu_vs": 77857,
-  "codegen.vredmin_vs": 77857,
-  "codegen.vredminu_vs": 77857,
-  "codegen.vredor_vs": 77857,
-  "codegen.vredsum_vs": 77857,
-  "codegen.vredxor_vs": 77857,
+  "codegen.vredand_vs": 77431,
+  "codegen.vredmax_vs": 77431,
+  "codegen.vredmaxu_vs": 77431,
+  "codegen.vredmin_vs": 77431,
+  "codegen.vredminu_vs": 77431,
+  "codegen.vredor_vs": 77431,
+  "codegen.vredsum_vs": 77431,
+  "codegen.vredxor_vs": 77431,
   "codegen.vrem_vv": 88287,
   "codegen.vrem_vx": 408214,
   "codegen.vremu_vv": 88419,
@@ -415,8 +415,8 @@
   "codegen.vwmulsu_vx": 164032,
   "codegen.vwmulu_vv": 42468,
   "codegen.vwmulu_vx": 164032,
-  "codegen.vwredsum_vs": 42814,
-  "codegen.vwredsumu_vs": 42814,
+  "codegen.vwredsum_vs": 42788,
+  "codegen.vwredsumu_vs": 42788,
   "codegen.vwsub_vv": 42445,
   "codegen.vwsub_vx": 138408,
   "codegen.vwsub_wv": 43527,

difftest/spike_interfaces/spike_interfaces.cc

@@ -22,26 +22,25 @@ cfg_t make_spike_cfg() {
   return cfg;
 }
 
-Spike::Spike(const char *set, const char *lvl,
-             size_t lane_number)
-    : sim(), isa(set, lvl), cfg(make_spike_cfg()),
-      proc(
-          /*isa*/ &isa,
-          /*cfg*/ &cfg,
-          /*sim*/ &sim,
-          /*id*/ 0,
-          /*halt on reset*/ true,
-          /*log_file_t*/ nullptr,
-          /*sout*/ std::cerr) {
+Spike::Spike(const char *set, const char *lvl, size_t lane_number,
+             size_t datapath_width)
+    : sim(), isa(set, lvl), cfg(make_spike_cfg()), proc(
+                                                       /*isa*/ &isa,
+                                                       /*cfg*/ &cfg,
+                                                       /*sim*/ &sim,
+                                                       /*id*/ 0,
+                                                       /*halt on reset*/ true,
+                                                       /*log_file_t*/ nullptr,
+                                                       /*sout*/ std::cerr) {
   proc.VU.lane_num = lane_number;
-  proc.VU.lane_granularity = 32;
+  proc.VU.lane_granularity = datapath_width;
 
   proc.enable_log_commits();
 }
 
-spike_t *spike_new(const char *set, const char *lvl,
-                   size_t lane_number) {
-  return new spike_t{new Spike(set, lvl, lane_number)};
+spike_t *spike_new(const char *set, const char *lvl, size_t lane_number,
+                   size_t datapath_width) {
+  return new spike_t{new Spike(set, lvl, lane_number, datapath_width)};
 }
 
 const char *proc_disassemble(spike_processor_t *proc) {

difftest/spike_interfaces/spike_interfaces.h

@@ -45,7 +45,8 @@ class t1_sim_t : public simif_t {
 
 class Spike {
 public:
-  Spike(const char *set, const char *lvl, size_t lane_number);
+  Spike(const char *set, const char *lvl, size_t lane_number,
+        size_t datapath_width);
   processor_t *get_proc() { return &proc; }
 
 private:

difftest/spike_interfaces/spike_interfaces_c.h

@@ -14,8 +14,8 @@ typedef struct spike_processor_t spike_processor_t;
 typedef struct spike_state_t spike_state_t;
 
 void spike_register_callback(void *ffi_target, ffi_callback callback);
-spike_t *spike_new(const char *set, const char *lvl,
-                   size_t lane_number);
+spike_t *spike_new(const char *set, const char *lvl, size_t lane_number,
+                   size_t datapath_width);
 const char *proc_disassemble(spike_processor_t *proc);
 void proc_reset(spike_processor_t *proc);
 spike_processor_t *spike_get_proc(spike_t *spike);

difftest/spike_rs/src/lib.rs

@@ -39,10 +39,16 @@ type FfiCallback = extern "C" fn(*mut (), u64) -> *mut u8;
 
 impl Spike {
   // we need to have a boxed SpikeCObject, since its pointer will be passed to C to perform FFI call
-  pub fn new(set: &str, lvl: &str, lane_number: usize, mem_size: usize) -> Box<Self> {
+  pub fn new(
+    set: &str,
+    lvl: &str,
+    lane_number: usize,
+    datapath_width: usize,
+    mem_size: usize,
+  ) -> Box<Self> {
     let set = CString::new(set).unwrap();
     let lvl = CString::new(lvl).unwrap();
-    let spike = unsafe { spike_new(set.as_ptr(), lvl.as_ptr(), lane_number) };
+    let spike = unsafe { spike_new(set.as_ptr(), lvl.as_ptr(), lane_number, datapath_width) };
     let mut self_: Box<Spike> = Box::new(Spike { spike, mem: vec![0; mem_size], size: mem_size });
 
     // TODO: support customized ffi
@@ -238,7 +244,12 @@ impl Drop for State {
 #[link(name = "spike_interfaces")]
 extern "C" {
   pub fn spike_register_callback(target: *mut (), callback: FfiCallback);
-  fn spike_new(set: *const c_char, lvl: *const c_char, lane_number: usize) -> *mut ();
+  fn spike_new(
+    set: *const c_char,
+    lvl: *const c_char,
+    lane_number: usize,
+    datapath_width: usize,
+  ) -> *mut ();
   fn spike_get_proc(spike: *mut ()) -> *mut ();
   fn spike_destruct(spike: *mut ());
   fn proc_disassemble(proc: *mut ()) -> *mut c_char;

difftest/spike_rs/src/runner.rs

@@ -67,7 +67,17 @@ pub struct SpikeArgs {
 impl SpikeArgs {
   fn to_spike_c_handler(&self) -> Box<Spike> {
     let lvl = "M";
-    Spike::new(&self.set, lvl, (self.dlen / 32) as usize, MEM_SIZE)
+
+    let data_width = 64;
+
+    // Create and return a new Spike instance
+    Spike::new(
+      &self.set,
+      lvl,
+      (self.dlen / data_width) as usize,
+      data_width as usize,
+      MEM_SIZE,
+    )
   }
 }
 

difftest/t1-sim-checker/src/t1emu/difftest.rs

@@ -24,15 +24,13 @@ pub fn diff(runner: &mut SpikeRunner, event: &JsonEvents) -> anyhow::Result<()>
       runner.cycle = *cycle;
       runner.update_lsu_idx(&LsuEnqEvent { enq: *enq, cycle: *cycle })
     }
-    JsonEvents::VrfWrite { issue_idx, vd, offset, mask, data, lane, cycle } => {
+    JsonEvents::VrfWrite { issue_idx, vrf_idx, mask, data, cycle } => {
       runner.cycle = *cycle;
       runner.peek_vrf_write(&VrfWriteEvent {
         issue_idx: *issue_idx,
-        vd: *vd,
-        offset: *offset,
+        vrf_idx: *vrf_idx,
         mask: mask.clone(),
         data: data.clone(),
-        lane: *lane,
         cycle: *cycle,
       })
     }

difftest/t1-sim-checker/src/t1emu/json_events.rs

@@ -55,13 +55,11 @@ pub(crate) enum JsonEvents {
   },
   VrfWrite {
     issue_idx: u8,
-    vd: u32,
-    offset: u32,
+    vrf_idx: usize,
     #[serde(deserialize_with = "str_to_vec_bool", default)]
     mask: Vec<bool>,
     #[serde(deserialize_with = "str_to_vec_u8", default)]
     data: Vec<u8>,
-    lane: u32,
     cycle: u64,
   },
   MemoryWrite {
@@ -98,12 +96,10 @@ pub struct LsuEnqEvent {
 }
 
 pub struct VrfWriteEvent {
-  pub lane: u32,
-  pub vd: u32,
-  pub offset: u32,
+  pub issue_idx: u8,
+  pub vrf_idx: usize,
   pub mask: Vec<bool>,
   pub data: Vec<u8>,
-  pub issue_idx: u8,
   pub cycle: u64,
 }
 
@@ -186,24 +182,17 @@ impl JsonEventRunner for SpikeRunner {
 
   fn peek_vrf_write(&mut self, vrf_write: &VrfWriteEvent) -> anyhow::Result<()> {
     let cycle = vrf_write.cycle;
-    let vlen_in_bytes = self.vlen / 8;
-    let lane_number = self.dlen / 32;
-    let record_idx_base = (vrf_write.vd * vlen_in_bytes
-      + (vrf_write.lane + lane_number * vrf_write.offset) * 4) as usize;
 
     let mut retire_issue: Option<u8> = None;
 
     if let Some(se) =
       self.commit_queue.iter_mut().rev().find(|se| se.issue_idx == vrf_write.issue_idx)
     {
       debug!(
-        "[{}] VrfWrite: lane={}, vd={}, idx_base={}, issue_idx={}, offset={}, mask={}, data={:x?} ({})",
+        "[{}] VrfWrite: issue_idx={}, idx_base={},  mask={}, data={:x?} ({})",
         vrf_write.cycle,
-        vrf_write.lane,
-        record_idx_base,
-        vrf_write.vd,
         vrf_write.issue_idx,
-        vrf_write.offset,
+        vrf_write.vrf_idx,
         mask_display(&vrf_write.mask),
         vrf_write.data,
         se.describe_insn()
@@ -228,46 +217,40 @@ impl JsonEventRunner for SpikeRunner {
       vrf_write.mask.iter().enumerate().filter(|(_, &mask)| mask).for_each(|(offset, _)| {
         let written_byte = *vrf_write.data.get(offset).unwrap_or(&0);
 
-        if let Some(record) = se.vrf_access_record.all_writes.get_mut(&(record_idx_base + offset)) {
+        if let Some(record) = se.vrf_access_record.all_writes.get_mut(&(vrf_write.vrf_idx + offset)) {
           assert_eq!(
             record.byte,
             written_byte,
             "[{}] VrfWrite: {offset}th byte incorrect ({:#02x} record != {written_byte:#02x} written) \
-              (lane={}, vd={}, offset={}, mask={}, data={:x?}) \
+              (mask={}, data={:x?}) \
               issue_idx={} [vrf_idx={}] (disasm: {}, pc: {:#x}, bits: {:#x})",
             vrf_write.cycle,
             record.byte,
-            vrf_write.lane,
-            vrf_write.vd,
-            vrf_write.offset,
             mask_display(&vrf_write.mask),
             vrf_write.data,
             se.issue_idx,
-            record_idx_base + offset,
+            vrf_write.vrf_idx + offset,
             se.disasm,
             se.pc,
             se.inst_bits
           );
           record.executed = true;
         } else {
           debug!(
-            "[{}] VrfWrite: cannot find vrf write record, maybe not changed (lane={}, vd={}, idx={}, offset={}, mask={}, data={:x?})",
+            "[{}] VrfWrite: cannot find vrf write record, maybe not changed (idx={}, mask={}, data={:x?})",
             vrf_write.cycle,
-            vrf_write.lane,
-            vrf_write.vd,
-            record_idx_base + offset,
-            vrf_write.offset,
+            vrf_write.vrf_idx + offset,
             mask_display(&vrf_write.mask),
             vrf_write.data
           );
         }
       })
     } else {
       info!(
-        "[{cycle}] VrfWrite: rtl detect vrf write on lane={}, vd={} \
+        "[{cycle}] VrfWrite: rtl detect vrf write on idx={} \
         with no matched se (issue_idx={}), \
         maybe from committed load insn",
-        vrf_write.lane, vrf_write.vd, vrf_write.issue_idx
+        vrf_write.vrf_idx, vrf_write.issue_idx
       );
     }
 

difftest/t1-sim-checker/src/t1rocketemu/difftest.rs

@@ -40,15 +40,13 @@ pub fn diff(runner: &mut SpikeRunner, event: &JsonEvents) -> anyhow::Result<()>
       runner.cycle = *cycle;
       runner.update_lsu_idx(&LsuEnqEvent { enq: *enq, cycle: *cycle })
     }
-    JsonEvents::VrfWrite { issue_idx, vd, offset, mask, data, lane, cycle } => {
+    JsonEvents::VrfWrite { issue_idx, vrf_idx, mask, data, cycle } => {
       runner.cycle = *cycle;
       runner.peek_vrf_write(&VrfWriteEvent {
         issue_idx: *issue_idx,
-        vd: *vd,
-        offset: *offset,
+        vrf_idx: *vrf_idx,
         mask: mask.clone(),
         data: data.clone(),
-        lane: *lane,
         cycle: *cycle,
       })
     }