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Adding support of +define+ in FileList. #1421

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merged 7 commits into from
Sep 3, 2022

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karimtera
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This PR implements: ParseSourceFileListFromCommandline(const std::vector<absl::string_view>& cmdline_args)
Which parses the command line arguments into a FileList that now contains a vector holding the definitions passed through +define+.

Note: ParseSourceFileListFromCommandline is not yet used in the preprocessor tool.

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Nice!

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ParseSourceFileListFromCommandline:
- Always uses absl::string_view unless we really need to copy the data.
- Added unit test containing defines, include directories, and source files.
'ParseSourceFileListFromCommandline()':
- Fix parsing issue.
- Add better error messages.
- Add more tests.

The preprocessor tool:
- Use 'ParseSourceFileListFromCommandline()' in subcommands.
@karimtera karimtera force-pushed the positional_arguments branch from 7250f04 to b1dcd93 Compare September 2, 2022 23:44
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There was an issue reported by @mglb in the original first PR, if the argument is +define+a=b=c, the macro value should be b=c, I added the fix in here, because I was afraid It will be lost in the first PR.

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hzeller commented Sep 3, 2022

did you also add a test to confirm that +define+a=b=c works ?

@karimtera
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Yup, I added a test for that.

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codecov-commenter commented Sep 3, 2022

Codecov Report

Merging #1421 (5ad2767) into master (fae1fd8) will decrease coverage by 0.01%.
The diff coverage is 88.70%.

@@            Coverage Diff             @@
##           master    #1421      +/-   ##
==========================================
- Coverage   92.94%   92.92%   -0.02%     
==========================================
  Files         342      342              
  Lines       24105    24158      +53     
==========================================
+ Hits        22404    22450      +46     
- Misses       1701     1708       +7     
Impacted Files Coverage Δ
verilog/tools/preprocessor/verilog_preprocessor.cc 89.65% <84.61%> (-2.27%) ⬇️
verilog/analysis/verilog_project.cc 94.44% <90.62%> (-0.74%) ⬇️
verilog/analysis/verilog_project.h 100.00% <100.00%> (ø)

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LGTM.
Do you want to add anything here, or want the TODO 'send defines to preprocessor' in follow-up changes ?

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LGTM. Do you want to add anything here, or want the TODO 'send defines to preprocessor' in follow-up changes ?

I've already done the 'send defines to preprocessor' in the the remaining PRs.

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hzeller commented Sep 3, 2022

Alright, so ready to merge ?

@karimtera
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Yes, ready to merge.

@hzeller hzeller merged commit 694974a into chipsalliance:master Sep 3, 2022
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hzeller commented Sep 3, 2022

Alright, it's in!

@karimtera karimtera deleted the positional_arguments branch September 3, 2022 02:38
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I will close PR #1373 then.

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hzeller commented Sep 6, 2022

To link this up: the corresponding issue is #1358

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3 participants