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[AArch64] Remove redundant FMOV for zero-extended i32/i16 loads to f64 #146920

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[AArch64] Remove redundant FMOV for zero-extended i32/i16 loads to f64 #146920

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[AArch64] Remove redundant FMOV for zero-extended i32/i16 loads to f64
Amichaxx Jul 4, 2025
0b3fd58
Merge branch 'main' into aarch64-load-opt
Amichaxx Jul 8, 2025
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10 changes: 9 additions & 1 deletion llvm/lib/Target/AArch64/AArch64InstrInfo.td
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Original file line number Diff line number Diff line change
Expand Up @@ -3924,6 +3924,14 @@ defm LDRSW : LoadUI<0b10, 0, 0b10, GPR64, uimm12s4, "ldrsw",
def : Pat<(i64 (zextloadi32 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))),
(SUBREG_TO_REG (i64 0), (LDRWui GPR64sp:$Rn, uimm12s4:$offset), sub_32)>;

// load zero-extended i32, bitcast to f64
def : Pat <(f64 (bitconvert (i64 (zextloadi32 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))))),
(SUBREG_TO_REG (i64 0), (LDRSui GPR64sp:$Rn, uimm12s4:$offset), ssub)>;

// load zero-extended i16, bitcast to f64
def : Pat <(f64 (bitconvert (i64 (zextloadi16 (am_indexed32 GPR64sp:$Rn, uimm12s2:$offset))))),
(SUBREG_TO_REG (i64 0), (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub)>;

// Pre-fetch.
def PRFMui : PrefetchUI<0b11, 0, 0b10, "prfm",
[(AArch64Prefetch timm:$Rt,
Expand Down Expand Up @@ -11012,4 +11020,4 @@ defm FMMLA : SIMDThreeSameVectorFP8MatrixMul<"fmmla">;
include "AArch64InstrAtomics.td"
include "AArch64SVEInstrInfo.td"
include "AArch64SMEInstrInfo.td"
include "AArch64InstrGISel.td"
include "AArch64InstrGISel.td"
15 changes: 15 additions & 0 deletions llvm/test/CodeGen/AArch64/load_u64_from_u16.ll
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@@ -0,0 +1,15 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=aarch64-linux-gnu -o - %s | FileCheck %s

define double @_Z9load_u64_from_u16_testPj(ptr %n){
; CHECK-LABEL: _Z9load_u64_from_u16_testPj:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldr h0, [x0]
; CHECK-NEXT: ret
entry:
%0 = load i16, ptr %n, align 2
%conv = zext i16 %0 to i64
%1 = bitcast i64 %conv to double
ret double %1
}

14 changes: 14 additions & 0 deletions llvm/test/CodeGen/AArch64/load_u64_from_u32.ll
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@@ -0,0 +1,14 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=aarch64-linux-gnu -o - %s | FileCheck %s

define double @_Z9load_u64_from_u32_testPj(ptr %n) {
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Can you add all of these as test cases: https://godbolt.org/z/4cPhr6f7e

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Yes, will get to adding these today. Thanks.

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They can probably be part of the same test file (and if you wanted to add tablegen patterns for all the types that would help keep them consistent). Otherwise this is looking good to me.

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Do you mind adding tests for each of the cases in the gobolt link (they can be in the same file). We might as well add patterns for all of them too, so that they all work the same.

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I have all the tests in the same file, as well as all matching patterns. I am waiting for internal approval before I can push. Thanks.

; CHECK-LABEL: _Z9load_u64_from_u32_testPj:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldr s0, [x0]
; CHECK-NEXT: ret
entry:
%0 = load i32, ptr %n, align 4
%conv = zext i32 %0 to i64
%1 = bitcast i64 %conv to double
ret double %1
}