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added spi 1-bit mode, code from litex #88

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added spi 1-bit mode, code from litex #88

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21 changes: 18 additions & 3 deletions misoc/cores/spi_flash.py
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Original file line number Diff line number Diff line change
Expand Up @@ -24,6 +24,11 @@ def _format_cmd(cmd, spi_width):
c &= ~(1<<(b*spi_width))
return c

class SpiIF(object):
def __init__(self, i, o, oe):
self.i = i
self.o = o
self.oe = oe

class SpiFlash(Module, AutoCSR):
def __init__(self, pads, dummy=15, div=2, with_bitbang=True):
Expand All @@ -35,7 +40,12 @@ def __init__(self, pads, dummy=15, div=2, with_bitbang=True):
Optionally supports software bitbanging (for write, erase, or other commands).
"""
self.bus = bus = wishbone.Interface()
spi_width = len(pads.dq)

if hasattr(pads, "mosi"):
spi_width = 1
else:
spi_width = len(pads.dq)

if with_bitbang:
self.bitbang = CSRStorage(4)
self.miso = CSRStatus()
Expand All @@ -59,8 +69,13 @@ def __init__(self, pads, dummy=15, div=2, with_bitbang=True):

pads.cs_n.reset = 1

dq = TSTriple(spi_width)
self.specials.dq = dq.get_tristate(pads.dq)
if spi_width > 1:
dq = TSTriple(spi_width)
self.specials.dq = dq.get_tristate(pads.dq)
else:
dq = SpiIF(pads.miso, pads.mosi, Signal())
assert with_bitbang == False, \
"Bitbang not supported with 1-bit SPI flash."
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Why not?

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Because it was not working out of the box because of this line:
https://github.com/m-labs/misoc/blob/master/misoc/cores/spi_flash.py#L85
so I didn't implement it.
If you can explain the code, I can try to implement it.


sr = Signal(max(cmd_width, addr_width, wbone_width))
self.comb += bus.dat_r.eq(sr)
Expand Down