Merged decoder (#17)

* Merge the decoder and adds Zce parameters * Update flist * Trimp trailing spaces and remove redundant comments * Run Verible on all SV files * Remove redndant comments and update march id * Rerun verible on all files
openhwgroup · Feb 17, 2022 · cf0ab06 · cf0ab06
1 parent d432b96
commit cf0ab06
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Showing 23 changed files with 3,599 additions and 3,492 deletions.
diff --git a/bhv/cv32e41p_apu_tracer.sv b/bhv/cv32e41p_apu_tracer.sv
@@ -52,7 +52,7 @@ module cv32e41p_apu_tracer (
 
   // open/close output file for writing
   initial begin
-    wait(rst_n == 1'b1);
+    wait (rst_n == 1'b1);
     $sformat(fn, "apu_trace_core_%h.log", hart_id_i);
     $display("[APU_TRACER] Output filename is: %s", fn);
     apu_trace = $fopen(fn, "w");

diff --git a/bhv/cv32e41p_instr_trace.svh b/bhv/cv32e41p_instr_trace.svh
@@ -48,20 +48,20 @@ typedef struct {
 } mem_acc_t;
 
 class instr_trace_t;
-  time         simtime;
-  int          cycles;
-  logic [31:0] pc;
-  logic [31:0] instr;
-  bit          compressed;
-  bit          wb_bypass;
-  bit          misaligned;
-  bit          retire;
-  bit          ebreak;
-  string       str;
-  reg_t        regs_read[$];
-  reg_t        regs_write[$];
-  mem_acc_t    mem_access[$];
-  logic        retired;
+  time             simtime;
+  int              cycles;
+  logic     [31:0] pc;
+  logic     [31:0] instr;
+  bit              compressed;
+  bit              wb_bypass;
+  bit              misaligned;
+  bit              retire;
+  bit              ebreak;
+  string           str;
+  reg_t            regs_read  [$];
+  reg_t            regs_write [$];
+  mem_acc_t        mem_access [$];
+  logic            retired;
 
   function new();
     str        = "";
@@ -359,9 +359,8 @@ class instr_trace_t;
       regs_read.push_back('{rs1, rs1_value, 0});
       regs_read.push_back('{rs2, rs2_value, 0});
       regs_write.push_back('{rd, 'x, 0});
-      str = $sformatf(
-          "%-16s x%0d, x%0d, x%0d, 0x%0d", mnemonic, rd, rs1, rs2, $unsigned(imm_s3_type[4:0])
-      );
+      str = $sformatf("%-16s x%0d, x%0d, x%0d, 0x%0d", mnemonic, rd, rs1, rs2,
+                      $unsigned(imm_s3_type[4:0]));
     end
   endfunction  // printAddNInstr
 
@@ -389,9 +388,8 @@ class instr_trace_t;
       regs_read.push_back('{rs2, rs2_value, 0});
       regs_read.push_back('{rs4, rs3_value, 0});
       regs_write.push_back('{rd, 'x, 0});
-      str = $sformatf(
-          "%-16s f%0d, f%0d, f%0d, f%0d", mnemonic, rd - 32, rs1 - 32, rs2 - 32, rs4 - 32
-      );
+      str = $sformatf("%-16s f%0d, f%0d, f%0d, f%0d", mnemonic, rd - 32, rs1 - 32, rs2 - 32,
+                      rs4 - 32);
     end
   endfunction  // printF3Instr
 

diff --git a/bhv/cv32e41p_wrapper.sv b/bhv/cv32e41p_wrapper.sv
@@ -28,18 +28,22 @@
 module cv32e41p_wrapper
   import cv32e41p_apu_core_pkg::*;
 #(
-    parameter PULP_XPULP          =  0,                   // PULP ISA Extension (incl. custom CSRs and hardware loop, excl. p.elw)
+    parameter PULP_XPULP          =  0,  // PULP ISA Extension (incl. custom CSRs and hardware loop, excl. p.elw)
     parameter PULP_CLUSTER = 0,  // PULP Cluster interface (incl. p.elw)
     parameter FPU = 0,  // Floating Point Unit (interfaced via APU interface)
     parameter PULP_ZFINX = 0,  // Float-in-General Purpose registers
+    parameter Zcea = 0,
+    parameter Zceb = 0,
+    parameter Zcec = 0,
+    parameter Zcee = 0,
     parameter NUM_MHPMCOUNTERS = 1
 ) (
     // Clock and Reset
     input logic clk_i,
     input logic rst_ni,
 
     input logic pulp_clock_en_i,  // PULP clock enable (only used if PULP_CLUSTER = 1)
-    input logic scan_cg_en_i,  // Enable all clock gates for testing
+    input logic scan_cg_en_i,     // Enable all clock gates for testing
 
     // Core ID, Cluster ID, debug mode halt address and boot address are considered more or less static
     input logic [31:0] boot_addr_i,
@@ -79,7 +83,7 @@ module cv32e41p_wrapper
     input  logic [APU_NUSFLAGS_CPU-1:0]       apu_flags_i,
 
     // Interrupt inputs
-    input  logic [31:0] irq_i,  // CLINT interrupts + CLINT extension interrupts
+    input  logic [31:0] irq_i,      // CLINT interrupts + CLINT extension interrupts
     output logic        irq_ack_o,
     output logic [ 4:0] irq_id_o,
 
@@ -144,7 +148,7 @@ module cv32e41p_wrapper
       .pc                (core_i.id_stage_i.pc_id_i),
       .instr             (core_i.id_stage_i.instr),
       .controller_state_i(core_i.id_stage_i.controller_i.ctrl_fsm_cs),
-      .compressed        (core_i.id_stage_i.is_compressed_i),
+      .compressed        (core_i.id_stage_i.is_compressed),
       .id_valid          (core_i.id_stage_i.id_valid_o),
       .is_decoding       (core_i.id_stage_i.is_decoding_o),
       .is_illegal        (core_i.id_stage_i.illegal_insn_dec),
@@ -204,6 +208,10 @@ module cv32e41p_wrapper
       .PULP_CLUSTER    (PULP_CLUSTER),
       .FPU             (FPU),
       .PULP_ZFINX      (PULP_ZFINX),
+      .Zcea            (Zcea),
+      .Zceb            (Zceb),
+      .Zcec            (Zcec),
+      .Zcee            (Zcee),
       .NUM_MHPMCOUNTERS(NUM_MHPMCOUNTERS)
   ) core_i (
       .*

diff --git a/cv32e41p_manifest.flist b/cv32e41p_manifest.flist
@@ -38,8 +38,7 @@ ${DESIGN_RTL_DIR}/cv32e41p_register_file_ff.sv
 ${DESIGN_RTL_DIR}/cv32e41p_load_store_unit.sv
 ${DESIGN_RTL_DIR}/cv32e41p_id_stage.sv
 ${DESIGN_RTL_DIR}/cv32e41p_aligner.sv
-${DESIGN_RTL_DIR}/cv32e41p_decoder.sv
-${DESIGN_RTL_DIR}/cv32e41p_compressed_decoder.sv
+${DESIGN_RTL_DIR}/cv32e41p_merged_decoder.sv
 ${DESIGN_RTL_DIR}/cv32e41p_fifo.sv
 ${DESIGN_RTL_DIR}/cv32e41p_prefetch_buffer.sv
 ${DESIGN_RTL_DIR}/cv32e41p_hwloop_regs.sv

diff --git a/rtl/cv32e41p_aligner.sv b/rtl/cv32e41p_aligner.sv
@@ -25,7 +25,7 @@ module cv32e41p_aligner (
     input logic rst_n,
 
     input  logic fetch_valid_i,
-    output logic aligner_ready_o,  //prevents overwriting the fethced instruction
+    output logic aligner_ready_o, //prevents overwriting the fethced instruction
 
     input logic if_valid_i,
 
@@ -34,7 +34,7 @@ module cv32e41p_aligner (
     output logic        instr_valid_o,
 
     input logic [31:0] branch_addr_i,
-    input logic        branch_i,  // Asserted if we are branching/jumping now
+    input logic        branch_i,       // Asserted if we are branching/jumping now
 
     input logic [31:0] hwlp_addr_i,
     input logic        hwlp_update_pc_i,

diff --git a/rtl/cv32e41p_alu.sv b/rtl/cv32e41p_alu.sv
@@ -263,36 +263,28 @@ module cv32e41p_alu
   // right shifts, we let the synthesizer optimize this
   logic [63:0] shift_op_a_32;
 
-  assign shift_op_a_32 = (operator_i == ALU_ROR) ? {
-        shift_op_a, shift_op_a
-      } : $signed(
-          {{32{shift_arithmetic & shift_op_a[31]}}, shift_op_a}
-      );
+  assign shift_op_a_32 = (operator_i == ALU_ROR) ? {shift_op_a, shift_op_a} : $signed(
+      {{32{shift_arithmetic & shift_op_a[31]}}, shift_op_a}
+  );
 
   always_comb begin
     case (vector_mode_i)
       VEC_MODE16: begin
-        shift_right_result[31:16] = $signed(
-            {shift_arithmetic & shift_op_a[31], shift_op_a[31:16]}
-        ) >>> shift_amt_int[19:16];
-        shift_right_result[15:0] = $signed(
-            {shift_arithmetic & shift_op_a[15], shift_op_a[15:0]}
-        ) >>> shift_amt_int[3:0];
+        shift_right_result[31:16] = $signed({shift_arithmetic & shift_op_a[31],
+                                             shift_op_a[31:16]}) >>> shift_amt_int[19:16];
+        shift_right_result[15:0] =
+            $signed({shift_arithmetic & shift_op_a[15], shift_op_a[15:0]}) >>> shift_amt_int[3:0];
       end
 
       VEC_MODE8: begin
-        shift_right_result[31:24] = $signed(
-            {shift_arithmetic & shift_op_a[31], shift_op_a[31:24]}
-        ) >>> shift_amt_int[26:24];
-        shift_right_result[23:16] = $signed(
-            {shift_arithmetic & shift_op_a[23], shift_op_a[23:16]}
-        ) >>> shift_amt_int[18:16];
-        shift_right_result[15:8] = $signed(
-            {shift_arithmetic & shift_op_a[15], shift_op_a[15:8]}
-        ) >>> shift_amt_int[10:8];
-        shift_right_result[7:0] = $signed(
-            {shift_arithmetic & shift_op_a[7], shift_op_a[7:0]}
-        ) >>> shift_amt_int[2:0];
+        shift_right_result[31:24] = $signed({shift_arithmetic & shift_op_a[31],
+                                             shift_op_a[31:24]}) >>> shift_amt_int[26:24];
+        shift_right_result[23:16] = $signed({shift_arithmetic & shift_op_a[23],
+                                             shift_op_a[23:16]}) >>> shift_amt_int[18:16];
+        shift_right_result[15:8] =
+            $signed({shift_arithmetic & shift_op_a[15], shift_op_a[15:8]}) >>> shift_amt_int[10:8];
+        shift_right_result[7:0] = $signed({shift_arithmetic & shift_op_a[7], shift_op_a[7:0]}) >>>
+            shift_amt_int[2:0];
       end
 
       default: // VEC_MODE32

diff --git a/rtl/cv32e41p_alu_div.sv b/rtl/cv32e41p_alu_div.sv
@@ -35,8 +35,8 @@ module cv32e41p_alu_div #(
     input  logic [C_LOG_WIDTH-1:0] OpBShift_DI,
     input  logic                   OpBIsZero_SI,
     //
-    input  logic                   OpBSign_SI,  // gate this to 0 in case of unsigned ops
-    input  logic [            1:0] OpCode_SI,  // 0: udiv, 2: urem, 1: div, 3: rem
+    input  logic                   OpBSign_SI,    // gate this to 0 in case of unsigned ops
+    input  logic [            1:0] OpCode_SI,     // 0: udiv, 2: urem, 1: div, 3: rem
     // handshake
     input  logic                   InVld_SI,
     // output IF
@@ -186,9 +186,9 @@ module cv32e41p_alu_div #(
 
   assign AReg_DN = (ARegEn_S) ? AddOut_D : AReg_DP;
   assign BReg_DN = (BRegEn_S) ? BMux_D : BReg_DP;
-  assign ResReg_DN = (LoadEn_S) ? '0 : (ResRegEn_S) ? {
-    ABComp_S, ResReg_DP[$high(ResReg_DP):1]
-  } : ResReg_DP;
+  assign ResReg_DN = (LoadEn_S) ? '0 : (ResRegEn_S) ? {ABComp_S, ResReg_DP[$high(
+      ResReg_DP
+  ):1]} : ResReg_DP;
 
   always_ff @(posedge Clk_CI or negedge Rst_RBI) begin : p_regs
     if (~Rst_RBI) begin