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Implement format-specific encoding mechanism #546

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  2. [DRAFT] Implement format-specific encoding mechanism

    The current instruction encoding mechanism for RISC-V in Sail uses a simple
    mapping, from “ast” to a 32-bit opcode value (ignoring compressed
    instructions for now). For example:
    ```
    union clause ast = RISCV_JALR : (bits(12), regidx, regidx)
    
    mapping clause encdec = RISCV_JALR(imm, rs1, rd)
      <-> imm @ rs1 @ 0b000 @ rd @ 0b1100111
    ```
    
    This is certainly functional.
    
    However, what’s missing from this representation is:
    - Any notion of the opcode format
    - Any enforcement mechanism for the order of the respective bit fields with
      respect to the opcode format
    - Any enforcement mechanism for the sizes of the respective bit fields
    
    A *wrong* encoding representation would readily compile:
    ```
    mapping clause encdec = RISCV_JALR(imm, rs1, rd)
      <-> 0b1100111 @ rd @ rs1 @ 0b000 @ imm /* WRONG */
    ```
    This would (hopefully) be caught in runtime testing, of course.
    
    This (draft) PR proposes an encoding mechanism with enhancements:
    - Each opcode is clearly associated with an encoding format
    - Each instruction only provides a structured list of encoding-agnostic opcode
      inputs
    - A format-specific, instruction-agnostic encoding mechanism is provided
    
    This forces instructions in the Sail code to clearly identify their formats,
    and allows them to provide the associated inputs for the encoding without
    concern for the specifics of the encoding.
    It also isolates the encoding scheme to a small set of format-specific encodings
    separate from the instruction definitions.
    
    An example for format-specific encoding:
    ```
    enum Format = { R_Format, U_Format, I_Format, J_Format, S_Format, B_Format, Unknown_Format }
    val opcode2format : bits(7) -> Format
    scattered function opcode2format
    
    union instruction_input = {
      IFormat: { imm: bits(12), rs1: regidx, funct3: bits(3), rd: regidx, opcode: bits(7) },
    [...]
    }
    
    val encdec : ast <-> instruction_input
    scattered mapping encdec
    
    mapping fmt2bits : instruction_input <-> bits(32) = {
      IFormat(struct { imm = imm, rs1 = rs1, funct3 = funct3, rd = rd, opcode = opcode }) if opcode2format(opcode) == I_Format
        <-> imm @ rs1 @ funct3 @ rd @ opcode if opcode2format(opcode) == I_Format,
    [...]
    }
    ```
    
    An example of a instruction’s encoding information:
    ```
    function clause opcode2format 0b1100111 = I_Format
    
    mapping clause encdec = RISCV_JALR(imm, rs1, rd)
      <-> IFormat(struct { imm = imm, rs1 = rs1, funct3 = 0b000, rd = rd, opcode = 0b1100111 })
    ```
    ThinkOpenly committed Sep 10, 2024
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  4. ruin run_tests.sh

    ThinkOpenly committed Sep 10, 2024
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