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Zcmp ext #610

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Zcmp ext #610

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520f019
Change sign to unsign in v extension
Yui5427 Oct 8, 2024
60f8ae6
Merge branch 'master' of https://github.com/rez5427/sail-riscv
Yui5427 Oct 10, 2024
d17a222
Merge branch 'master' of https://github.com/rez5427/sail-riscv
Yui5427 Oct 18, 2024
9be19c6
Merge branch 'master' of https://github.com/rez5427/sail-riscv
Yui5427 Oct 19, 2024
c031994
remove register vlenb
Yui5427 Oct 25, 2024
f122037
Merge branch 'riscv:master' into master
rez5427 Oct 25, 2024
23698cb
Revert "remove register vlenb"
Yui5427 Oct 25, 2024
2179dd4
Add cm.push
Yui5427 Nov 3, 2024
5792198
Add cm.pop
Yui5427 Nov 3, 2024
cead192
Add cm.popret cm.popretz
Yui5427 Nov 4, 2024
499b93b
Add cm.popret cm.popretz
Yui5427 Nov 4, 2024
b2e8ddb
Add cm.mvsa01 cm.mva01s and some changes
Yui5427 Nov 6, 2024
eb47018
Refactor code to conform to community standards
Yui5427 Nov 7, 2024
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1 change: 1 addition & 0 deletions Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -24,6 +24,7 @@ SAIL_CHECK_SRCS = riscv_addr_checks_common.sail riscv_addr_checks.sail riscv_mis
SAIL_DEFAULT_INST = riscv_insts_base.sail riscv_insts_zifencei.sail riscv_insts_aext.sail riscv_insts_zca.sail riscv_insts_mext.sail riscv_insts_zicsr.sail riscv_insts_hints.sail
SAIL_DEFAULT_INST += riscv_insts_fext.sail riscv_insts_zcf.sail
SAIL_DEFAULT_INST += riscv_insts_dext.sail riscv_insts_zcd.sail
SAIL_DEFAULT_INST += riscv_insts_zcmp.sail

SAIL_DEFAULT_INST += riscv_insts_svinval.sail

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