Sunflower Full-System Hardware Emulator and Physical System Simulator for Sensor-Driven Systems. Built-in architecture modeling of Hitachi SH (j-core), RISC-V, and more.

FRISC processor simulator in JavaScript

Super scalar Processor design

A simulation of the Tomasulo algorithm, a hardware algorithm for out-of-order scheduling and execution of computer instructions, written in C++.

Modular Graphical Simulator for Teaching Microprogramming

Common-Lisp simulation and FPGA implementation of MIT's Scheme-79 chip

Single Bus Processor - Summer Project 2016

A C++ pipeline based simulator of RSIC architecture.

MIPS Pipelined CPU simulation using VHDL language

2021-22 Summer Project in Computer Science

CZ3001 Advanced Computer Architecture, AY 2015-16 Semester 1

An 8-bit processor in VHDL based on a simple instruction set

Processor emulator with assembler-type code

An imaginary 16-bit CPU architecture with custom assembly language and instructions

💻 MIPS Pipeline Processor simulator

SST Juno Processor Model

A superscalar out-of‐order architectural simulator (With Memory Hierarchy).

cross-plateform RISC-V emulator

A 6502 Microprocessor (accurately W65C02S) Simulator.