Configurable, high-performance FFT hardware IP core for ASIC/FPGA. Pipelined radix-2 DIF, 256–4096-point support, 16-bit fixed-point, double-buffered memory, APB/AXI interfaces. Optimized for throughput and low latency.

MLow Codec

🧩 Starter template for ASIC hardware IP blocks with Vyges metadata, OpenLane integration, and comprehensive documentation

Programmable ADC IP with Cadence PDK support, featuring behavioral models, comprehensive testbenches, and automated verification flows for mixed-signal design.

SPI master controller with APB interface, multi-mode support (all SPI modes), configurable FIFO, and interrupt features for ASIC/FPGA integration.

A configurable full adder IP with three implementation approaches (simple XOR/AND, modular half adder, carry lookahead) following Vyges conventions. Includes comprehensive verification with SystemVerilog, UVM, and Cocotb testbenches supporting multiple simulators (Icarus, Verilator, Questa, VCS, Xcelium). Production-ready for ASIC/FPGA w/ 500MHz

Configurable PWM controller with multiple channels and precise frequency control

A fully pipelined digital Hilbert transformer IP block for DSP applications including single sideband modulation, amplitude/phase detection, and quadrature signal processing. Optimized for FPGA and ASIC implementations with configurable precision and maximum throughput.

A configurable UART controller IP with APB interface, FIFO support, and interrupt capabilities. Designed for SkyWater 130nm Open Source PDK with comprehensive verification and OpenLane integration.