PWM Controller IP - Quickstart

Overview

This repository contains a configurable, multi-channel PWM controller IP core, ready for SoC, FPGA, and chiplet integration. It supports APB4, precise frequency/duty/phase control, and advanced safety features.

Directory Structure

• rtl/ - SystemVerilog RTL source
• tb/ - Testbenches (SystemVerilog and cocotb)
• integration/ - Wrappers and example top-levels for SoC, FPGA, chiplet
• flow/openlane/ - OpenLane ASIC flow config
• flow/vivado/ - Vivado FPGA flow scripts
• docs/ - Design spec and documentation

Simulation (Verilator/SystemVerilog)

# Example: Run SystemVerilog testbench
cd tb/
make -f Makefile sv_tb
# Or run with Verilator
make -f Makefile verilator

Simulation (Python/cocotb)

cd tb/cocotb/
make

ASIC Synthesis (OpenLane)

cd flow/openlane/
# Edit config.json as needed
make

FPGA Synthesis (Vivado)

cd flow/vivado/
vivado -mode batch -source create_project.tcl

Example Integration

• SoC/Simulation: See integration/example_soc_top.v for APB master + PWM
• FPGA: See integration/example_fpga_top.v for board-level instantiation
• Chiplet: See integration/example_chiplet_top.v for die-to-die integration

APB Register Map

See docs/PWM-Controller_design_spec.md for full register and interface details.

Support

For questions, open an issue or contact the Vyges IP team.