A tool for compression of lookup tables and generation of their hardware files in Verilog for RTL designs
A tool to generate optimized hardware files for univariate functions.
Configurable, high-performance FFT hardware IP core for ASIC/FPGA. Pipelined radix-2 DIF, 256–4096-point support, 16-bit fixed-point, double-buffered memory, APB/AXI interfaces. Optimized for throughput and low latency.
🏗️ Central hub for Vyges community discussions, issues, feature requests, and collaboration
🧩 Starter template for FPGA hardware IP blocks with Vyges metadata and comprehensive documentation
A fully pipelined digital Hilbert transformer IP block for DSP applications including single sideband modulation, amplitude/phase detection, and quadrature signal processing. Optimized for FPGA and ASIC implementations with configurable precision and maximum throughput.
A configurable UART controller IP with APB interface, FIFO support, and interrupt capabilities. Designed for SkyWater 130nm Open Source PDK with comprehensive verification and OpenLane integration.
📋 Vyges Metadata Specification - Standardized format for hardware IP discovery and integration
🧩 Starter template for ASIC hardware IP blocks with Vyges metadata, OpenLane integration, and comprehensive documentation
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