5-Stage-pipline_RISCV-CPU

Name		Name	Last commit message	Last commit date
Latest commit History 60 Commits
RVC_Extension		RVC_Extension
branch_in_ex		branch_in_ex
cache		cache
final_version		final_version
riscv20190617		riscv20190617
62178982_342220433155240_6674716796773203968_n.jpg		62178982_342220433155240_6674716796773203968_n.jpg
BPU.v		BPU.v
CHIP.v		CHIP.v
CONTROL_UNIT.v		CONTROL_UNIT.v
Compress_methods.v		Compress_methods.v
DECOMPRESSIONUNIT.v		DECOMPRESSIONUNIT.v
DSDHW3_RISCV.v		DSDHW3_RISCV.v
DecompTB.v		DecompTB.v
FORWARDING_UNIT.v		FORWARDING_UNIT.v
Final_tb.v		Final_tb.v
HAZARD_DETECTION_UNIT.v		HAZARD_DETECTION_UNIT.v
README.md		README.md
RISCV_hasHazard.v		RISCV_hasHazard.v
RISCV_noHazard.v		RISCV_noHazard.v
Report.pdf		Report.pdf
cache_2way.v		cache_2way.v
cache_dm.v		cache_dm.v
cache_dm_ro.v		cache_dm_ro.v

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